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List: dri-patches
Subject: drm: Branch 'master' - 3 commits
From: darktama () kemper ! freedesktop ! org (Ben Skeggs)
Date: 2008-03-23 16:19:12
Message-ID: 20080323161912.5A8DC10096 () kemper ! freedesktop ! org
[Download RAW message or body]
linux-core/Makefile.kernel | 2
linux-core/nouveau_bo.c | 305 ++++++++++++++++++++++++++++++++++++++++++++
linux-core/nouveau_buffer.c | 299 -------------------------------------------
shared-core/nv40_graph.c | 124 ++++++-----------
4 files changed, 353 insertions(+), 377 deletions(-)
New commits:
commit a244d2905052d3263bdcc26b295558a354702b89
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Mar 24 03:22:42 2008 +1100
nouveau: silence warning
diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel
index defbe43..f012262 100644
--- a/linux-core/Makefile.kernel
+++ b/linux-core/Makefile.kernel
@@ -23,7 +23,7 @@ i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \
i915_buffer.o i915_compat.o i915_execbuf.o
nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
nouveau_object.o nouveau_irq.o nouveau_notifier.o nouveau_swmthd.o \
- nouveau_sgdma.o nouveau_dma.o nouveau_buffer.o nouveau_fence.o \
+ nouveau_sgdma.o nouveau_dma.o nouveau_bo.o nouveau_fence.o \
nv04_timer.o \
nv04_mc.o nv40_mc.o nv50_mc.o \
nv04_fb.o nv10_fb.o nv40_fb.o \
diff --git a/linux-core/nouveau_bo.c b/linux-core/nouveau_bo.c
new file mode 100644
index 0000000..7a89976
--- /dev/null
+++ b/linux-core/nouveau_bo.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2007 Dave Airlied
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Authors: Dave Airlied <airlied@linux.ie>
+ * Ben Skeggs <darktama@iinet.net.au>
+ * Jeremy Kolb <jkolb@brandeis.edu>
+ */
+
+#include "drmP.h"
+#include "nouveau_drm.h"
+#include "nouveau_drv.h"
+#include "nouveau_dma.h"
+
+static struct drm_ttm_backend *
+nouveau_bo_create_ttm_backend_entry(struct drm_device * dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ switch (dev_priv->gart_info.type) {
+ case NOUVEAU_GART_AGP:
+ return drm_agp_init_ttm(dev);
+ case NOUVEAU_GART_SGDMA:
+ return nouveau_sgdma_init_ttm(dev);
+ default:
+ DRM_ERROR("Unknown GART type %d\n", dev_priv->gart_info.type);
+ break;
+ }
+
+ return NULL;
+}
+
+static int
+nouveau_bo_fence_type(struct drm_buffer_object *bo,
+ uint32_t *fclass, uint32_t *type)
+{
+ /* When we get called, *fclass is set to the requested fence class */
+
+ if (bo->mem.proposed_flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE))
+ *type = 3;
+ else
+ *type = 1;
+ return 0;
+
+}
+
+static int
+nouveau_bo_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags)
+{
+ /* We'll do this from user space. */
+ return 0;
+}
+
+static int
+nouveau_bo_init_mem_type(struct drm_device *dev, uint32_t type,
+ struct drm_mem_type_manager *man)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ switch (type) {
+ case DRM_BO_MEM_LOCAL:
+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
+ _DRM_FLAG_MEMTYPE_CACHED;
+ man->drm_bus_maptype = 0;
+ break;
+ case DRM_BO_MEM_VRAM:
+ man->flags = _DRM_FLAG_MEMTYPE_FIXED |
+ _DRM_FLAG_MEMTYPE_MAPPABLE |
+ _DRM_FLAG_NEEDS_IOREMAP;
+ man->io_addr = NULL;
+ man->drm_bus_maptype = _DRM_FRAME_BUFFER;
+ man->io_offset = drm_get_resource_start(dev, 1);
+ man->io_size = drm_get_resource_len(dev, 1);
+ if (man->io_size > nouveau_mem_fb_amount(dev))
+ man->io_size = nouveau_mem_fb_amount(dev);
+ break;
+ case DRM_BO_MEM_PRIV0:
+ /* Unmappable VRAM */
+ man->flags = _DRM_FLAG_MEMTYPE_CMA;
+ man->drm_bus_maptype = 0;
+ break;
+ case DRM_BO_MEM_TT:
+ switch (dev_priv->gart_info.type) {
+ case NOUVEAU_GART_AGP:
+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
+ _DRM_FLAG_MEMTYPE_CSELECT |
+ _DRM_FLAG_NEEDS_IOREMAP;
+ man->drm_bus_maptype = _DRM_AGP;
+ break;
+ case NOUVEAU_GART_SGDMA:
+ man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
+ _DRM_FLAG_MEMTYPE_CSELECT |
+ _DRM_FLAG_MEMTYPE_CMA;
+ man->drm_bus_maptype = _DRM_SCATTER_GATHER;
+ break;
+ default:
+ DRM_ERROR("Unknown GART type: %d\n",
+ dev_priv->gart_info.type);
+ return -EINVAL;
+ }
+
+ man->io_offset = dev_priv->gart_info.aper_base;
+ man->io_size = dev_priv->gart_info.aper_size;
+ man->io_addr = NULL;
+ break;
+ default:
+ DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static uint64_t
+nouveau_bo_evict_flags(struct drm_buffer_object *bo)
+{
+ switch (bo->mem.mem_type) {
+ case DRM_BO_MEM_LOCAL:
+ case DRM_BO_MEM_TT:
+ return DRM_BO_FLAG_MEM_LOCAL;
+ default:
+ return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
+ }
+ return 0;
+}
+
+
+/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
+ * DRM_BO_MEM_{VRAM,PRIV0,TT} directly.
+ */
+static int
+nouveau_bo_move_m2mf(struct drm_buffer_object *bo, int evict, int no_wait,
+ struct drm_bo_mem_reg *new_mem)
+{
+ struct drm_device *dev = bo->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_drm_channel *dchan = &dev_priv->channel;
+ struct drm_bo_mem_reg *old_mem = &bo->mem;
+ uint32_t srch, dsth, page_count;
+
+ /* Can happen during init/takedown */
+ if (!dchan->chan)
+ return -EINVAL;
+
+ srch = old_mem->mem_type == DRM_BO_MEM_TT ? NvDmaTT : NvDmaFB;
+ dsth = new_mem->mem_type == DRM_BO_MEM_TT ? NvDmaTT : NvDmaFB;
+ if (srch != dchan->m2mf_dma_source || dsth != dchan->m2mf_dma_destin) {
+ dchan->m2mf_dma_source = srch;
+ dchan->m2mf_dma_destin = dsth;
+
+ BEGIN_RING(NvSubM2MF,
+ NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_SOURCE, 2);
+ OUT_RING (dchan->m2mf_dma_source);
+ OUT_RING (dchan->m2mf_dma_destin);
+ }
+
+ page_count = new_mem->num_pages;
+ while (page_count) {
+ int line_count = (page_count > 2047) ? 2047 : page_count;
+
+ BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
+ OUT_RING (old_mem->mm_node->start << PAGE_SHIFT);
+ OUT_RING (new_mem->mm_node->start << PAGE_SHIFT);
+ OUT_RING (PAGE_SIZE); /* src_pitch */
+ OUT_RING (PAGE_SIZE); /* dst_pitch */
+ OUT_RING (PAGE_SIZE); /* line_length */
+ OUT_RING (line_count);
+ OUT_RING ((1<<8)|(1<<0));
+ OUT_RING (0);
+ BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
+ OUT_RING (0);
+
+ page_count -= line_count;
+ }
+
+ return drm_bo_move_accel_cleanup(bo, evict, no_wait, dchan->chan->id,
+ DRM_FENCE_TYPE_EXE, 0, new_mem);
+}
+
+/* Flip pages into the GART and move if we can. */
+static int
+nouveau_bo_move_gart(struct drm_buffer_object *bo, int evict, int no_wait,
+ struct drm_bo_mem_reg *new_mem)
+{
+ struct drm_device *dev = bo->dev;
+ struct drm_bo_mem_reg tmp_mem;
+ int ret;
+
+ tmp_mem = *new_mem;
+ tmp_mem.mm_node = NULL;
+ tmp_mem.proposed_flags = (DRM_BO_FLAG_MEM_TT |
+ DRM_BO_FLAG_CACHED |
+ DRM_BO_FLAG_FORCE_CACHING);
+
+ ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
+
+ if (ret)
+ return ret;
+
+ ret = drm_ttm_bind (bo->ttm, &tmp_mem);
+ if (ret)
+ goto out_cleanup;
+
+ ret = nouveau_bo_move_m2mf(bo, 1, no_wait, &tmp_mem);
+ if (ret)
+ goto out_cleanup;
+
+ ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);
+
+out_cleanup:
+ if (tmp_mem.mm_node) {
+ mutex_lock(&dev->struct_mutex);
+ if (tmp_mem.mm_node != bo->pinned_node)
+ drm_mm_put_block(tmp_mem.mm_node);
+ tmp_mem.mm_node = NULL;
+ mutex_unlock(&dev->struct_mutex);
+ }
+ return ret;
+}
+
+static int
+nouveau_bo_move(struct drm_buffer_object *bo, int evict, int no_wait,
+ struct drm_bo_mem_reg *new_mem)
+{
+ struct drm_bo_mem_reg *old_mem = &bo->mem;
+
+ if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
+ if (old_mem->mem_type == DRM_BO_MEM_LOCAL)
+ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+#if 0
+ if (!nouveau_bo_move_to_gart(bo, evict, no_wait, new_mem))
+#endif
+ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+ }
+ else
+ if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
+#if 0
+ if (nouveau_bo_move_to_gart(bo, evict, no_wait, new_mem))
+#endif
+ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+ }
+ else {
+// if (nouveau_bo_move_m2mf(bo, evict, no_wait, new_mem))
+ return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+ }
+
+ if (0) {
+ nouveau_bo_move_m2mf(bo, 0, 0, NULL);
+ nouveau_bo_move_gart(bo, 0, 0, NULL);
+ }
+
+ return 0;
+}
+
+static void
+nouveau_bo_flush_ttm(struct drm_ttm *ttm)
+{
+}
+
+static uint32_t nouveau_mem_prios[] = {
+ DRM_BO_MEM_PRIV0,
+ DRM_BO_MEM_VRAM,
+ DRM_BO_MEM_TT,
+ DRM_BO_MEM_LOCAL
+};
+static uint32_t nouveau_busy_prios[] = {
+ DRM_BO_MEM_TT,
+ DRM_BO_MEM_PRIV0,
+ DRM_BO_MEM_VRAM,
+ DRM_BO_MEM_LOCAL
+};
+
+struct drm_bo_driver nouveau_bo_driver = {
+ .mem_type_prio = nouveau_mem_prios,
+ .mem_busy_prio = nouveau_busy_prios,
+ .num_mem_type_prio = sizeof(nouveau_mem_prios)/sizeof(uint32_t),
+ .num_mem_busy_prio = sizeof(nouveau_busy_prios)/sizeof(uint32_t),
+ .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
+ .fence_type = nouveau_bo_fence_type,
+ .invalidate_caches = nouveau_bo_invalidate_caches,
+ .init_mem_type = nouveau_bo_init_mem_type,
+ .evict_flags = nouveau_bo_evict_flags,
+ .move = nouveau_bo_move,
+ .ttm_cache_flush= nouveau_bo_flush_ttm,
+ .command_stream_barrier = NULL
+};
diff --git a/linux-core/nouveau_buffer.c b/linux-core/nouveau_buffer.c
deleted file mode 100644
index 1154931..0000000
--- a/linux-core/nouveau_buffer.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Copyright 2007 Dave Airlied
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-/*
- * Authors: Dave Airlied <airlied@linux.ie>
- * Ben Skeggs <darktama@iinet.net.au>
- * Jeremy Kolb <jkolb@brandeis.edu>
- */
-
-#include "drmP.h"
-#include "nouveau_drm.h"
-#include "nouveau_drv.h"
-#include "nouveau_dma.h"
-
-static struct drm_ttm_backend *
-nouveau_bo_create_ttm_backend_entry(struct drm_device * dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- switch (dev_priv->gart_info.type) {
- case NOUVEAU_GART_AGP:
- return drm_agp_init_ttm(dev);
- case NOUVEAU_GART_SGDMA:
- return nouveau_sgdma_init_ttm(dev);
- default:
- DRM_ERROR("Unknown GART type %d\n", dev_priv->gart_info.type);
- break;
- }
-
- return NULL;
-}
-
-static int
-nouveau_bo_fence_type(struct drm_buffer_object *bo,
- uint32_t *fclass, uint32_t *type)
-{
- /* When we get called, *fclass is set to the requested fence class */
-
- if (bo->mem.proposed_flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE))
- *type = 3;
- else
- *type = 1;
- return 0;
-
-}
-
-static int
-nouveau_bo_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags)
-{
- /* We'll do this from user space. */
- return 0;
-}
-
-static int
-nouveau_bo_init_mem_type(struct drm_device *dev, uint32_t type,
- struct drm_mem_type_manager *man)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- switch (type) {
- case DRM_BO_MEM_LOCAL:
- man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
- _DRM_FLAG_MEMTYPE_CACHED;
- man->drm_bus_maptype = 0;
- break;
- case DRM_BO_MEM_VRAM:
- man->flags = _DRM_FLAG_MEMTYPE_FIXED |
- _DRM_FLAG_MEMTYPE_MAPPABLE |
- _DRM_FLAG_NEEDS_IOREMAP;
- man->io_addr = NULL;
- man->drm_bus_maptype = _DRM_FRAME_BUFFER;
- man->io_offset = drm_get_resource_start(dev, 1);
- man->io_size = drm_get_resource_len(dev, 1);
- if (man->io_size > nouveau_mem_fb_amount(dev))
- man->io_size = nouveau_mem_fb_amount(dev);
- break;
- case DRM_BO_MEM_PRIV0:
- /* Unmappable VRAM */
- man->flags = _DRM_FLAG_MEMTYPE_CMA;
- man->drm_bus_maptype = 0;
- break;
- case DRM_BO_MEM_TT:
- switch (dev_priv->gart_info.type) {
- case NOUVEAU_GART_AGP:
- man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
- _DRM_FLAG_MEMTYPE_CSELECT |
- _DRM_FLAG_NEEDS_IOREMAP;
- man->drm_bus_maptype = _DRM_AGP;
- break;
- case NOUVEAU_GART_SGDMA:
- man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
- _DRM_FLAG_MEMTYPE_CSELECT |
- _DRM_FLAG_MEMTYPE_CMA;
- man->drm_bus_maptype = _DRM_SCATTER_GATHER;
- break;
- default:
- DRM_ERROR("Unknown GART type: %d\n",
- dev_priv->gart_info.type);
- return -EINVAL;
- }
-
- man->io_offset = dev_priv->gart_info.aper_base;
- man->io_size = dev_priv->gart_info.aper_size;
- man->io_addr = NULL;
- break;
- default:
- DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
- return -EINVAL;
- }
- return 0;
-}
-
-static uint64_t
-nouveau_bo_evict_flags(struct drm_buffer_object *bo)
-{
- switch (bo->mem.mem_type) {
- case DRM_BO_MEM_LOCAL:
- case DRM_BO_MEM_TT:
- return DRM_BO_FLAG_MEM_LOCAL;
- default:
- return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
- }
- return 0;
-}
-
-
-/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
- * DRM_BO_MEM_{VRAM,PRIV0,TT} directly.
- */
-static int
-nouveau_bo_move_m2mf(struct drm_buffer_object *bo, int evict, int no_wait,
- struct drm_bo_mem_reg *new_mem)
-{
- struct drm_device *dev = bo->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_drm_channel *dchan = &dev_priv->channel;
- struct drm_bo_mem_reg *old_mem = &bo->mem;
- uint32_t srch, dsth, page_count;
-
- /* Can happen during init/takedown */
- if (!dchan->chan)
- return -EINVAL;
-
- srch = old_mem->mem_type == DRM_BO_MEM_TT ? NvDmaTT : NvDmaFB;
- dsth = new_mem->mem_type == DRM_BO_MEM_TT ? NvDmaTT : NvDmaFB;
- if (srch != dchan->m2mf_dma_source || dsth != dchan->m2mf_dma_destin) {
- dchan->m2mf_dma_source = srch;
- dchan->m2mf_dma_destin = dsth;
-
- BEGIN_RING(NvSubM2MF,
- NV_MEMORY_TO_MEMORY_FORMAT_SET_DMA_SOURCE, 2);
- OUT_RING (dchan->m2mf_dma_source);
- OUT_RING (dchan->m2mf_dma_destin);
- }
-
- page_count = new_mem->num_pages;
- while (page_count) {
- int line_count = (page_count > 2047) ? 2047 : page_count;
-
- BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
- OUT_RING (old_mem->mm_node->start << PAGE_SHIFT);
- OUT_RING (new_mem->mm_node->start << PAGE_SHIFT);
- OUT_RING (PAGE_SIZE); /* src_pitch */
- OUT_RING (PAGE_SIZE); /* dst_pitch */
- OUT_RING (PAGE_SIZE); /* line_length */
- OUT_RING (line_count);
- OUT_RING ((1<<8)|(1<<0));
- OUT_RING (0);
- BEGIN_RING(NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
- OUT_RING (0);
-
- page_count -= line_count;
- }
-
- return drm_bo_move_accel_cleanup(bo, evict, no_wait, dchan->chan->id,
- DRM_FENCE_TYPE_EXE, 0, new_mem);
-}
-
-/* Flip pages into the GART and move if we can. */
-static int
-nouveau_bo_move_gart(struct drm_buffer_object *bo, int evict, int no_wait,
- struct drm_bo_mem_reg *new_mem)
-{
- struct drm_device *dev = bo->dev;
- struct drm_bo_mem_reg tmp_mem;
- int ret;
-
- tmp_mem = *new_mem;
- tmp_mem.mm_node = NULL;
- tmp_mem.proposed_flags = (DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_FORCE_CACHING);
-
- ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
-
- if (ret)
- return ret;
-
- ret = drm_ttm_bind (bo->ttm, &tmp_mem);
- if (ret)
- goto out_cleanup;
-
- ret = nouveau_bo_move_m2mf(bo, 1, no_wait, &tmp_mem);
- if (ret)
- goto out_cleanup;
-
- ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);
-
-out_cleanup:
- if (tmp_mem.mm_node) {
- mutex_lock(&dev->struct_mutex);
- if (tmp_mem.mm_node != bo->pinned_node)
- drm_mm_put_block(tmp_mem.mm_node);
- tmp_mem.mm_node = NULL;
- mutex_unlock(&dev->struct_mutex);
- }
- return ret;
-}
-
-static int
-nouveau_bo_move(struct drm_buffer_object *bo, int evict, int no_wait,
- struct drm_bo_mem_reg *new_mem)
-{
- struct drm_bo_mem_reg *old_mem = &bo->mem;
-
- if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
- if (old_mem->mem_type == DRM_BO_MEM_LOCAL)
- return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
-#if 0
- if (!nouveau_bo_move_to_gart(bo, evict, no_wait, new_mem))
-#endif
- return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
- }
- else
- if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
-#if 0
- if (nouveau_bo_move_to_gart(bo, evict, no_wait, new_mem))
-#endif
- return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
- }
- else {
-// if (nouveau_bo_move_m2mf(bo, evict, no_wait, new_mem))
- return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
- }
- return 0;
-}
-
-static void
-nouveau_bo_flush_ttm(struct drm_ttm *ttm)
-{
-}
-
-static uint32_t nouveau_mem_prios[] = {
- DRM_BO_MEM_PRIV0,
- DRM_BO_MEM_VRAM,
- DRM_BO_MEM_TT,
- DRM_BO_MEM_LOCAL
-};
-static uint32_t nouveau_busy_prios[] = {
- DRM_BO_MEM_TT,
- DRM_BO_MEM_PRIV0,
- DRM_BO_MEM_VRAM,
- DRM_BO_MEM_LOCAL
-};
-
-struct drm_bo_driver nouveau_bo_driver = {
- .mem_type_prio = nouveau_mem_prios,
- .mem_busy_prio = nouveau_busy_prios,
- .num_mem_type_prio = sizeof(nouveau_mem_prios)/sizeof(uint32_t),
- .num_mem_busy_prio = sizeof(nouveau_busy_prios)/sizeof(uint32_t),
- .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
- .fence_type = nouveau_bo_fence_type,
- .invalidate_caches = nouveau_bo_invalidate_caches,
- .init_mem_type = nouveau_bo_init_mem_type,
- .evict_flags = nouveau_bo_evict_flags,
- .move = nouveau_bo_move,
- .ttm_cache_flush= nouveau_bo_flush_ttm,
- .command_stream_barrier = NULL
-};
commit 24ba0c9c3bd0f160eb0c3a820fd407998f85fd55
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Mar 24 03:20:59 2008 +1100
nv40: voodoo - not quite.
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 3e47bba..2540fc5 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -1617,25 +1617,12 @@ nv40_graph_load_context(struct nouveau_channel *chan)
return 0;
}
-/* Some voodoo that makes context switching work without the binary driver
- * initialising the card first.
- *
- * It is possible to effect how the context is saved from PGRAPH into a block
- * of instance memory by altering the values in these tables. This may mean
- * that the context layout of each chipset is slightly different (at least
- * NV40 and C51 are different). It would also be possible for chipsets to
- * have an identical context layout, but pull the data from different PGRAPH
- * registers.
- *
- * TODO: decode the meaning of the magic values, may provide clues about the
- * differences between the various NV40 chipsets.
- * TODO: one we have a better idea of how each chipset differs, perhaps think
- * about unifying these instead of providing a separate table for each
- * chip.
- *
- * mmio-trace dumps from other nv4x/g7x/c5x cards very welcome :)
+/* These blocks of "magic numbers" are actually a microcode that the GPU uses
+ * to control how graphics contexts get saved and restored between PRAMIN
+ * and PGRAPH during a context switch. We're currently using values seen
+ * in mmio-traces of the binary driver.
*/
-static uint32_t nv40_ctx_voodoo[] = {
+static uint32_t nv40_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409406,
0x0040a268, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
@@ -1667,7 +1654,7 @@ static uint32_t nv40_ctx_voodoo[] = {
~0
};
-static uint32_t nv41_ctx_voodoo[] = {
+static uint32_t nv41_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306,
0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
@@ -1698,7 +1685,7 @@ static uint32_t nv41_ctx_voodoo[] = {
0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
};
-static uint32_t nv43_ctx_voodoo[] = {
+static uint32_t nv43_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06,
0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
@@ -1731,7 +1718,7 @@ static uint32_t nv43_ctx_voodoo[] = {
~0
};
-static uint32_t nv44_ctx_voodoo[] = {
+static uint32_t nv44_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409a65, 0x00409f06,
0x0040ac68, 0x0040248f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
@@ -1764,7 +1751,7 @@ static uint32_t nv44_ctx_voodoo[] = {
0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
};
-static uint32_t nv46_ctx_voodoo[] = {
+static uint32_t nv46_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306,
0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
@@ -1795,7 +1782,7 @@ static uint32_t nv46_ctx_voodoo[] = {
0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
};
-static uint32_t nv47_ctx_voodoo[] = {
+static uint32_t nv47_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409265, 0x00409606,
0x0040a368, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
@@ -1828,7 +1815,7 @@ static uint32_t nv47_ctx_voodoo[] = {
};
//this is used for nv49 and nv4b
-static uint32_t nv49_4b_ctx_voodoo[] ={
+static uint32_t nv49_4b_ctx_prog[] ={
0x00400564, 0x00400505, 0x00408165, 0x00408206, 0x00409e68, 0x00200020,
0x0060000a, 0x00700080, 0x00104042, 0x00200020, 0x0060000a, 0x00700000,
0x001040c5, 0x00400f26, 0x00401068, 0x0060000d, 0x0070008f, 0x0070000e,
@@ -1860,7 +1847,7 @@ static uint32_t nv49_4b_ctx_voodoo[] ={
};
-static uint32_t nv4a_ctx_voodoo[] = {
+static uint32_t nv4a_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06,
0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
@@ -1893,7 +1880,7 @@ static uint32_t nv4a_ctx_voodoo[] = {
0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
};
-static uint32_t nv4c_ctx_voodoo[] = {
+static uint32_t nv4c_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409065, 0x00409406,
0x0040a168, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
@@ -1924,7 +1911,7 @@ static uint32_t nv4c_ctx_voodoo[] = {
0x0040a405, 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
};
-static uint32_t nv4e_ctx_voodoo[] = {
+static uint32_t nv4e_ctx_prog[] = {
0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06,
0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
@@ -1971,7 +1958,7 @@ nv40_graph_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv =
(struct drm_nouveau_private *)dev->dev_private;
- uint32_t *ctx_voodoo;
+ uint32_t *ctx_prog;
uint32_t vramsz, tmp;
int i, j;
@@ -1981,34 +1968,34 @@ nv40_graph_init(struct drm_device *dev)
NV_PMC_ENABLE_PGRAPH);
switch (dev_priv->chipset) {
- case 0x40: ctx_voodoo = nv40_ctx_voodoo; break;
+ case 0x40: ctx_prog = nv40_ctx_prog; break;
case 0x41:
- case 0x42: ctx_voodoo = nv41_ctx_voodoo; break;
- case 0x43: ctx_voodoo = nv43_ctx_voodoo; break;
- case 0x44: ctx_voodoo = nv44_ctx_voodoo; break;
- case 0x46: ctx_voodoo = nv46_ctx_voodoo; break;
- case 0x47: ctx_voodoo = nv47_ctx_voodoo; break;
- case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break;
- case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;
- case 0x4b: ctx_voodoo = nv49_4b_ctx_voodoo; break;
+ case 0x42: ctx_prog = nv41_ctx_prog; break;
+ case 0x43: ctx_prog = nv43_ctx_prog; break;
+ case 0x44: ctx_prog = nv44_ctx_prog; break;
+ case 0x46: ctx_prog = nv46_ctx_prog; break;
+ case 0x47: ctx_prog = nv47_ctx_prog; break;
+ case 0x49: ctx_prog = nv49_4b_ctx_prog; break;
+ case 0x4a: ctx_prog = nv4a_ctx_prog; break;
+ case 0x4b: ctx_prog = nv49_4b_ctx_prog; break;
case 0x4c:
- case 0x67: ctx_voodoo = nv4c_ctx_voodoo; break;
- case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;
+ case 0x67: ctx_prog = nv4c_ctx_prog; break;
+ case 0x4e: ctx_prog = nv4e_ctx_prog; break;
default:
- DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n",
- dev_priv->chipset);
- ctx_voodoo = NULL;
+ DRM_ERROR("Context program for 0x%02x unavailable\n",
+ dev_priv->chipset);
+ ctx_prog = NULL;
break;
}
- /* Load the context voodoo onto the card */
- if (ctx_voodoo) {
- DRM_DEBUG("Loading context-switch voodoo\n");
+ /* Load the context program onto the card */
+ if (ctx_prog) {
+ DRM_DEBUG("Loading context program\n");
i = 0;
NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
- while (ctx_voodoo[i] != ~0) {
- NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_voodoo[i]);
+ while (ctx_prog[i] != ~0) {
+ NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_prog[i]);
i++;
}
}
commit 6f4b3de284e93e8fdb133f0aadfc86d298f45916
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Mar 24 03:13:05 2008 +1100
nv40: allocate massive amount of PRAMIN for grctx on all chipsets.
More or less a workaround for issues on some chipsets where a context
switch results in critical data in PRAMIN being overwritten by the GPU.
The correct fix is known, but may take some time before it's a feasible
option.
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 6ef02bf..3e47bba 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -28,22 +28,6 @@
#include "drm.h"
#include "nouveau_drv.h"
-/* The sizes are taken from the difference between the start of two
- * grctx addresses while running the nvidia driver. Probably slightly
- * larger than they actually are, because of other objects being created
- * between the contexts
- */
-#define NV40_GRCTX_SIZE (175*1024)
-#define NV41_GRCTX_SIZE (92*1024)
-#define NV43_GRCTX_SIZE (70*1024)
-#define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */
-#define NV47_GRCTX_SIZE (125*1024)
-#define NV49_GRCTX_SIZE (164640)
-#define NV4A_GRCTX_SIZE (64*1024)
-#define NV4B_GRCTX_SIZE (164640)
-#define NV4C_GRCTX_SIZE (25*1024)
-#define NV4E_GRCTX_SIZE (25*1024)
-
/*TODO: deciper what each offset in the context represents. The below
* contexts are taken from dumps just after the 3D object is
* created.
@@ -1471,61 +1455,60 @@ nv40_graph_create_context(struct nouveau_channel *chan)
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
- unsigned int ctx_size;
int ret;
+ /* These functions populate the graphics context with a whole heap
+ * of default state. All these functions are very similar, with
+ * a minimal amount of chipset-specific changes. However, as we're
+ * currently dependant on the context programs used by the NVIDIA
+ * binary driver these functions must match the layout expected by
+ * them. Hopefully at some point this will all change.
+ */
switch (dev_priv->chipset) {
case 0x40:
- ctx_size = NV40_GRCTX_SIZE;
ctx_init = nv40_graph_context_init;
break;
case 0x41:
case 0x42:
- ctx_size = NV41_GRCTX_SIZE;
ctx_init = nv41_graph_context_init;
break;
case 0x43:
- ctx_size = NV43_GRCTX_SIZE;
ctx_init = nv43_graph_context_init;
break;
case 0x46:
- ctx_size = NV46_GRCTX_SIZE;
ctx_init = nv46_graph_context_init;
break;
case 0x47:
- DRM_INFO("NV47 warning: If your card behaves strangely, please come to the irc channel\n");
- ctx_size = NV47_GRCTX_SIZE;
ctx_init = nv47_graph_context_init;
break;
case 0x49:
- ctx_size = NV49_GRCTX_SIZE;
ctx_init = nv49_graph_context_init;
break;
case 0x44:
case 0x4a:
- ctx_size = NV4A_GRCTX_SIZE;
ctx_init = nv4a_graph_context_init;
break;
case 0x4b:
- ctx_size = NV4B_GRCTX_SIZE;
ctx_init = nv4b_graph_context_init;
break;
case 0x4c:
case 0x67:
- ctx_size = NV4C_GRCTX_SIZE;
ctx_init = nv4c_graph_context_init;
break;
case 0x4e:
- ctx_size = NV4E_GRCTX_SIZE;
ctx_init = nv4e_graph_context_init;
break;
default:
- ctx_size = NV40_GRCTX_SIZE;
ctx_init = nv40_graph_context_init;
break;
}
- if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
+ /* Allocate a 175KiB block of PRAMIN to store the context. This
+ * is massive overkill for a lot of chipsets, but it should be safe
+ * until we're able to implement this properly (will happen at more
+ * or less the same time we're able to write our own context programs.
+ */
+ if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 175*1024, 16,
NVOBJ_FLAG_ZERO_ALLOC,
&chan->ramin_grctx)))
return ret;
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