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List: dri-patches
Subject: drm: Branch 'master' - 7 commits
From: darktama () kemper ! freedesktop ! org (Ben Skeggs)
Date: 2008-01-07 15:19:16
Message-ID: 20080107151916.2A14210096 () kemper ! freedesktop ! org
[Download RAW message or body]
linux-core/nouveau_sgdma.c | 24 +++++------
shared-core/nouveau_state.c | 7 +--
shared-core/nv50_fifo.c | 92 ++++++++++++++++++++++----------------------
shared-core/nv50_graph.c | 56 +++++++++++++++-----------
shared-core/nv50_instmem.c | 4 +
5 files changed, 99 insertions(+), 84 deletions(-)
New commits:
commit 0bfd09f719fb1de3e489fe513a122f29cdcef0c3
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Jan 7 18:56:44 2008 +1100
nv50: more small changes
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c
index 6a138c2..503f45d 100644
--- a/shared-core/nv50_graph.c
+++ b/shared-core/nv50_graph.c
@@ -49,6 +49,7 @@ nv50_graph_init_intr(struct drm_device *dev)
DRM_DEBUG("\n");
NV_WRITE(NV03_PGRAPH_INTR, 0xffffffff);
+ NV_WRITE(0x400138, 0xffffffff);
NV_WRITE(NV40_PGRAPH_INTR_EN, 0xffffffff);
}
@@ -310,7 +311,7 @@ nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
DRM_DEBUG("inst=0x%08x, save=%d\n", inst, save);
old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
- NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst | (1<<31));
+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
NV_WRITE(0x400824, NV_READ(0x400824) |
(save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
@@ -337,7 +338,7 @@ nv50_graph_load_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31));
+ uint32_t inst = chan->ramin->instance >> 12;
int ret; (void)ret;
DRM_DEBUG("ch%d\n", chan->id);
@@ -349,7 +350,7 @@ nv50_graph_load_context(struct nouveau_channel *chan)
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
NV_WRITE(0x400320, 4);
- NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst);
+ NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst | (1<<31));
return 0;
}
@@ -358,7 +359,7 @@ int
nv50_graph_save_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
- uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31));
+ uint32_t inst = chan->ramin->instance >> 12;
DRM_DEBUG("ch%d\n", chan->id);
commit 942b500e24fba25e3e047c7756b75a2782076512
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Jan 7 18:18:51 2008 +1100
nv50: oops, lost some state saving along the way somewhere.
xf86-video-nv will now work again after nouveau.
diff --git a/shared-core/nv50_instmem.c b/shared-core/nv50_instmem.c
index c80574a..9687ecb 100644
--- a/shared-core/nv50_instmem.c
+++ b/shared-core/nv50_instmem.c
@@ -69,6 +69,10 @@ nv50_instmem_init(struct drm_device *dev)
return -ENOMEM;
dev_priv->Engine.instmem.priv = priv;
+ /* Save state, will restore at takedown. */
+ for (i = 0x1700; i <= 0x1710; i+=4)
+ priv->save1700[(i-0x1700)/4] = NV_READ(i);
+
/* Reserve the last MiB of VRAM, we should probably try to avoid
* setting up the below tables over the top of the VBIOS image at
* some point.
commit 3d248cd7e4538ced5c0b652a784eb4ef309d5e11
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Jan 7 17:23:31 2008 +1100
nv50: hook up timer funcs...
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index 7535360..8fe128c 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -88,7 +88,6 @@ static int nouveau_init_card_mappings(struct drm_device *dev)
static int nouveau_stub_init(struct drm_device *dev) { return 0; }
static void nouveau_stub_takedown(struct drm_device *dev) {}
-static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; }
static int nouveau_init_engine_ptrs(struct drm_device *dev)
{
@@ -251,9 +250,9 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->instmem.unbind = nv50_instmem_unbind;
engine->mc.init = nv50_mc_init;
engine->mc.takedown = nv50_mc_takedown;
- engine->timer.init = nouveau_stub_init;
- engine->timer.read = nouveau_stub_timer_read;
- engine->timer.takedown = nouveau_stub_takedown;
+ engine->timer.init = nv04_timer_init;
+ engine->timer.read = nv04_timer_read;
+ engine->timer.takedown = nv04_timer_takedown;
engine->fb.init = nouveau_stub_init;
engine->fb.takedown = nouveau_stub_takedown;
engine->graph.init = nv50_graph_init;
commit 7a4ba7273c740503b6f254f74b2e06312c15790a
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Jan 7 17:10:36 2008 +1100
nv50: abort on chips without ctx ucode
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c
index 1698cef..6a138c2 100644
--- a/shared-core/nv50_graph.c
+++ b/shared-core/nv50_graph.c
@@ -186,7 +186,7 @@ static uint32_t nv86_ctx_voodoo[] = {
0x0070001c, 0x0060000c, ~0
};
-static void
+static int
nv50_graph_init_ctxctl(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -203,32 +203,37 @@ nv50_graph_init_ctxctl(struct drm_device *dev)
break;
default:
DRM_ERROR("no voodoo for chipset NV%02x\n", dev_priv->chipset);
- break;
+ return -EINVAL;
}
- if (voodoo) {
- NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
- while (*voodoo != ~0) {
- NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo);
- voodoo++;
- }
+ NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+ while (*voodoo != ~0) {
+ NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo);
+ voodoo++;
}
NV_WRITE(0x400320, 4);
NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
+
+ return 0;
}
int
nv50_graph_init(struct drm_device *dev)
{
+ int ret;
+
DRM_DEBUG("\n");
nv50_graph_init_reset(dev);
nv50_graph_init_intr(dev);
nv50_graph_init_regs__nv(dev);
nv50_graph_init_regs(dev);
- nv50_graph_init_ctxctl(dev);
+
+ ret = nv50_graph_init_ctxctl(dev);
+ if (ret)
+ return ret;
return 0;
}
commit 15f8fd34df11d9fceb3f813c9478ffe66cae3473
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Jan 7 17:07:59 2008 +1100
nv50: some needed ctx vals
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c
index 6d1413e..1698cef 100644
--- a/shared-core/nv50_graph.c
+++ b/shared-core/nv50_graph.c
@@ -272,6 +272,10 @@ nv50_graph_create_context(struct nouveau_channel *chan)
return ret;
}
+ INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x00000/4,
+ chan->ramin->instance >> 12);
+ INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x0011c/4, 0x00000002);
+
return 0;
}
commit fa5e18679fcdb7bd2d69c605183b0b205416bf2b
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Jan 7 16:55:20 2008 +1100
nv50: use dummy page in gart tables
Just to be safe, we don't really know exactly how the tables work yet, so
we can't be certain there's a way to say "page not present".
diff --git a/linux-core/nouveau_sgdma.c b/linux-core/nouveau_sgdma.c
index 6c61819..cc4d5a9 100644
--- a/linux-core/nouveau_sgdma.c
+++ b/linux-core/nouveau_sgdma.c
@@ -139,8 +139,8 @@ nouveau_sgdma_unbind(struct drm_ttm_backend *be)
if (dev_priv->card_type < NV_50) {
INSTANCE_WR(gpuobj, pte, pteval | 3);
} else {
- INSTANCE_WR(gpuobj, (pte<<1)+0, 0x00000010);
- INSTANCE_WR(gpuobj, (pte<<1)+1, 0x00000004);
+ INSTANCE_WR(gpuobj, (pte<<1)+0, pteval | 0x21);
+ INSTANCE_WR(gpuobj, (pte<<1)+1, 0x00000000);
}
pte++;
@@ -221,15 +221,14 @@ nouveau_sgdma_init(struct drm_device *dev)
return ret;
}
- if (dev_priv->card_type < NV_50) {
- dev_priv->gart_info.sg_dummy_page =
- alloc_page(GFP_KERNEL|__GFP_DMA32);
- SetPageLocked(dev_priv->gart_info.sg_dummy_page);
- dev_priv->gart_info.sg_dummy_bus =
- pci_map_page(dev->pdev,
- dev_priv->gart_info.sg_dummy_page, 0,
- PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ dev_priv->gart_info.sg_dummy_page =
+ alloc_page(GFP_KERNEL|__GFP_DMA32);
+ SetPageLocked(dev_priv->gart_info.sg_dummy_page);
+ dev_priv->gart_info.sg_dummy_bus =
+ pci_map_page(dev->pdev, dev_priv->gart_info.sg_dummy_page, 0,
+ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ if (dev_priv->card_type < NV_50) {
/* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and
* confirmed to work on c51. Perhaps means NV_DMA_TARGET_PCIE
* on those cards? */
@@ -245,8 +244,9 @@ nouveau_sgdma_init(struct drm_device *dev)
}
} else {
for (i=0; i<obj_size; i+=8) {
- INSTANCE_WR(gpuobj, (i+0)/4, 0); //x00000010);
- INSTANCE_WR(gpuobj, (i+4)/4, 0); //0x00000004);
+ INSTANCE_WR(gpuobj, (i+0)/4,
+ dev_priv->gart_info.sg_dummy_bus | 0x21);
+ INSTANCE_WR(gpuobj, (i+4)/4, 0);
}
}
commit 3d3d509dcae7f26cfcbe63e527a16f181a24e37c
Author: Ben Skeggs <skeggsb@gmail.com>
Date: Mon Jan 7 16:52:47 2008 +1100
nv50: some cleanups + small changes
diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c
index c5cde91..edf4edb 100644
--- a/shared-core/nv50_fifo.c
+++ b/shared-core/nv50_fifo.c
@@ -28,9 +28,10 @@
#include "drm.h"
#include "nouveau_drv.h"
-typedef struct {
- struct nouveau_gpuobj_ref *thingo;
-} nv50_fifo_priv;
+struct nv50_fifo_priv {
+ struct nouveau_gpuobj_ref *thingo[2];
+ int cur_thingo;
+};
#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
@@ -38,23 +39,23 @@ static void
nv50_fifo_init_thingo(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
- struct nouveau_gpuobj_ref *thingo = priv->thingo;
- int i, fi=2;
+ struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
+ struct nouveau_gpuobj_ref *cur;
+ int i, nr;
DRM_DEBUG("\n");
- INSTANCE_WR(thingo->gpuobj, 0, 0x7e);
- INSTANCE_WR(thingo->gpuobj, 1, 0x7e);
- for (i = 1; i < 127; i++, fi) {
+ cur = priv->thingo[priv->cur_thingo];
+ priv->cur_thingo = !priv->cur_thingo;
+
+ /* We never schedule channel 0 or 127 */
+ for (i = 1, nr = 0; i < 127; i++) {
if (dev_priv->fifos[i]) {
- INSTANCE_WR(thingo->gpuobj, fi, i);
- fi++;
+ INSTANCE_WR(cur->gpuobj, nr++, i);
}
}
-
- NV_WRITE(0x32f4, thingo->instance >> 12);
- NV_WRITE(0x32ec, fi);
+ NV_WRITE(0x32f4, cur->instance >> 12);
+ NV_WRITE(0x32ec, nr);
NV_WRITE(0x2500, 0x101);
}
@@ -98,14 +99,12 @@ static void
nv50_fifo_init_reset(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- uint32_t pmc_e;
+ uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
DRM_DEBUG("\n");
- pmc_e = NV_READ(NV03_PMC_ENABLE);
- NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO);
- pmc_e = NV_READ(NV03_PMC_ENABLE);
- NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO);
+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
}
static void
@@ -141,7 +140,7 @@ nv50_fifo_init_regs__nv(struct drm_device *dev)
NV_WRITE(0x250c, 0x6f3cfc34);
}
-static int
+static void
nv50_fifo_init_regs(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -158,15 +157,13 @@ nv50_fifo_init_regs(struct drm_device *dev)
/* Enable dummy channels setup by nv50_instmem.c */
nv50_fifo_channel_enable(dev, 0, 1);
nv50_fifo_channel_enable(dev, 127, 1);
-
- return 0;
}
int
nv50_fifo_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- nv50_fifo_priv *priv;
+ struct nv50_fifo_priv *priv;
int ret;
DRM_DEBUG("\n");
@@ -179,18 +176,23 @@ nv50_fifo_init(struct drm_device *dev)
nv50_fifo_init_reset(dev);
nv50_fifo_init_intr(dev);
- if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000,
- NVOBJ_FLAG_ZERO_ALLOC,
- &priv->thingo))) {
- DRM_ERROR("error creating thingo: %d\n", ret);
+ ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[0]);
+ if (ret) {
+ DRM_ERROR("error creating thingo0: %d\n", ret);
return ret;
}
- nv50_fifo_init_context_table(dev);
+ ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[1]);
+ if (ret) {
+ DRM_ERROR("error creating thingo1: %d\n", ret);
+ return ret;
+ }
+ nv50_fifo_init_context_table(dev);
nv50_fifo_init_regs__nv(dev);
- if ((ret = nv50_fifo_init_regs(dev)))
- return ret;
+ nv50_fifo_init_regs(dev);
return 0;
}
@@ -199,14 +201,15 @@ void
nv50_fifo_takedown(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
+ struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
DRM_DEBUG("\n");
if (!priv)
return;
- nouveau_gpuobj_ref_del(dev, &priv->thingo);
+ nouveau_gpuobj_ref_del(dev, &priv->thingo[0]);
+ nouveau_gpuobj_ref_del(dev, &priv->thingo[1]);
dev_priv->Engine.fifo.priv = NULL;
drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
@@ -234,18 +237,18 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
if (IS_G80) {
uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
- if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset,
- vram_offset, 0x100,
- NVOBJ_FLAG_ZERO_ALLOC |
- NVOBJ_FLAG_ZERO_FREE,
- &ramfc, &chan->ramfc)))
- return ret;
+ ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, vram_offset,
+ 0x100, NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE, &ramfc,
+ &chan->ramfc);
+ if (ret)
+ return ret;
} else {
- if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100,
- 256,
- NVOBJ_FLAG_ZERO_ALLOC |
- NVOBJ_FLAG_ZERO_FREE,
- &chan->ramfc)))
+ ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256,
+ NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE,
+ &chan->ramfc);
+ if (ret)
return ret;
ramfc = chan->ramfc->gpuobj;
}
@@ -272,7 +275,8 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12);
}
- if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) {
+ ret = nv50_fifo_channel_enable(dev, chan->id, 0);
+ if (ret) {
DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret);
nouveau_gpuobj_ref_del(dev, &chan->ramfc);
return ret;
diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c
index e398cfc..6d1413e 100644
--- a/shared-core/nv50_graph.c
+++ b/shared-core/nv50_graph.c
@@ -34,14 +34,12 @@ static void
nv50_graph_init_reset(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- uint32_t pmc_e;
+ uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
DRM_DEBUG("\n");
- pmc_e = NV_READ(NV03_PMC_ENABLE);
- NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PGRAPH);
- pmc_e = NV_READ(NV03_PMC_ENABLE);
- NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PGRAPH);
+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
}
static void
@@ -253,11 +251,10 @@ nv50_graph_create_context(struct nouveau_channel *chan)
DRM_DEBUG("ch%d\n", chan->id);
- if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
- grctx_size, 0x1000,
- NVOBJ_FLAG_ZERO_ALLOC |
- NVOBJ_FLAG_ZERO_FREE,
- &chan->ramin_grctx)))
+ ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
+ if (ret)
return ret;
hdr = IS_G80 ? 0x200 : 0x20;
@@ -269,7 +266,8 @@ nv50_graph_create_context(struct nouveau_channel *chan)
INSTANCE_WR(ramin, (hdr + 0x10)/4, 0);
INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000);
- if ((ret = engine->graph.load_context(chan))) {
+ ret = engine->graph.load_context(chan);
+ if (ret) {
DRM_ERROR("Error hacking up initial context: %d\n", ret);
return ret;
}
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