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List:       dri-devel
Subject:    Re: [PATCH] drm/etnaviv: fix DMA direction handling for cached read/write buffers
From:       Daniel Stone <daniel () fooishbar ! org>
Date:       2024-01-29 10:29:08
Message-ID: CAPj87rNOMYS7g_bU8Xjmh9xEJhuzG+BViXakC7wzgiDaG+9yCg () mail ! gmail ! com
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Hi Lucas,

On Fri, 26 Jan 2024 at 17:00, Lucas Stach <l.stach@pengutronix.de> wrote:
> The dma sync operation needs to be done with DMA_BIDIRECTIONAL when
> the BO is prepared for both read and write operations. With the
> current inverted if ladder it would only be synced for DMA_FROM_DEVICE.
>
> [...]
>
>  static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op)
>  {
> -       if (op & ETNA_PREP_READ)
> +       if (op & (ETNA_PREP_READ | ETNA_PREP_WRITE))
> +               return DMA_BIDIRECTIONAL;

This test will always be true for _either_ read or write.

Cheers,
Daniel
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