From dri-devel  Wed Jun 28 04:02:43 2023
From: Lucas De Marchi <lucas.demarchi () intel ! com>
Date: Wed, 28 Jun 2023 04:02:43 +0000
To: dri-devel
Subject: Re: [PATCH v2 6/6] drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER
Message-Id: <xk7u2ucaymz6t6fs4ldqnnoz4iyvweavbzurevsnaaof75jddc () gtdsrbqtxcvx>
X-MARC-Message: https://marc.info/?l=dri-devel&m=168792515708025

On Tue, Jun 27, 2023 at 11:30:26AM -0700, Kenneth Graunke wrote:
>On Saturday, June 24, 2023 10:17:57 AM PDT Lucas De Marchi wrote:
>> The comment on the parameter being 0 to avoid the read back doesn't
>> apply as this is not a call to wa_mcr_add(), but rather to
>> wa_mcr_clr_set(). So, this register is actually checked and it's
>> according to the Bspec that the register is RW, not RO.
>
>I think you mean wa_add and wa_write_clr_set here (not mcr).
>
>One thing I've been confused about while reading this code:
>
>static void
>wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
>{
>        wa_add(wal, reg, clear, set, clear, false);
>}
>
>The second to last parameter is read_mask aka wa->read.  We're
>initializing it to the...bits to clear.  (I would think it should be
>(clear | set) to pick up all modified bits.)
>
>wa_verify seems to balk at ((cur ^ wa->set) & wa->read).  But...if
>wa->read is just the clear mask, that wouldn't actually verify that
>any bits were set at all.  Or am I misunderstanding something?
>
>If not, we may be failing to verify the majority of our workarounds :(

I can see it failing in some cases, but it should pass in the majority.
I think there's an issue when the clr bits are not a super set of the
set bits. For example, this works:

clr=0xf, set=1

This is what happens when we are setting a field. However it would fail
to verify for cases in which we have, .e.g

clr=0x1, set=0, i.e. we are just clearing one bit. Since wa->read in
this case would be 0, it wouldn't matter if cur is 0 or 1. It seems like
commit eeec73f8a4a4 ("drm/i915/gt: Skip rmw for masked registers")
is the one who broke it. Setting read_mask to set | clr seems to
suffice as then we would get any inconsistencies between what was read
from the bits that should be set.

thanks
Lucas De Marchi

>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 848519b58e45..5fe85fad91c1 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -666,7 +666,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>  	/* Wa_1604278689:icl,ehl */
>>  	wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
>>  	wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,
>> -			 0, /* write-only register; skip validation */
>> +			 0,
>>  			 0xFFFFFFFF);
>>
>>  	/* Wa_1406306137:icl,ehl */
>
>In this particular example, since clear bits are 0, I don't think any
>verification is happening at all.
>
>--Ken