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List:       classiccmp
Subject:    Re: on FPGA simulation
From:       Philipp Hachtmann <hachti () hachti ! de>
Date:       2011-11-28 12:12:01
Message-ID: 4ED37A91.9030902 () hachti ! de
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Am 18.11.2011 02:26, schrieb David Riley:
> you actually know what the implications are and accept them, it's
> fine (as with so many things that are "no-nos" in engineering).

Couldn't have been said better!

In VHDL I mix signal and variable assignments in processes. I've been 
told *NEVER* to do that because it leads to unpredictable results - 
wrong, you just have to understand what's going on. Then it's perfectly 
save to mix variable and signal assignments.

:-)

Philipp
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