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List:       busybox
Subject:    [BusyBox] Atomic Increment/Decrement on PowerPC
From:       "Michael N. Moran" <mike () mnmoran ! org>
Date:       2005-06-20 20:44:03
Message-ID: 42B72A93.80004 () mnmoran ! org
[Download RAW message or body]

While perusing the code in the "shell/ash.c" file, I
noticed the INTOFF, SAVEINT, RESTOREINT, and EXSIGON
macros.

Do these macros (and the other uses of the suppressint
variable) expect the increments and decrements of the
suppressint variable to be atomic? This is a part of
the signal handling code, so expect this is true.

If so, then these are broken for PowerPC and other RISC
architectures, since these will generate a three instruction
load-modify-store sequence that is not atomic.

The correct way to do this for PowerPC involves the lwarx
(load with reservation) and stwcx. (store conditional) in
a loop.

This IBM PowerPC article describes the issue as it relates
to sig_atomic_t.

http://www-128.ibm.com/developerworks/library/pa-atom/

Examples of implementations include the GLIBC
"sysdeps/powerpc/atomicity.h" atomic_add function,
which looks something like this:

__attribute__ ((unused))
atomic_add (volatile uint32_t *mem, int val)
   {
     int tmp;
    __asm__ ("\
   0:	lwarx	%0,0,%1
	add%I2	%0,%0,%2
   	stwcx.	%0,0,%1
   	bne-	0b
" : "=&b"(tmp) : "r" (mem), "Ir"(val) : "cr0", "memory");
   }

My guess is that BusyBox could use the GLIBC version
of this function, and I believe that the
"uClib/include/atomic.h" file even defines
atomic_increment and atomic_decrement in terms of atomic_add.

-- 
Michael N. Moran           (h) 770 516 7918
5009 Old Field Ct.         (c) 678 521 5460
Kennesaw, GA, USA 30144    http://mnmoran.org

"So often times it happens, that we live our lives in chains
   and we never even know we have the key."
The Eagles, "Already Gone"

The Beatles were wrong: 1 & 1 & 1 is 1





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