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List: bochs-cvs
Subject: [Bochs-cvs] [13498] trunk/bochs/bios
From: vruppert--- via Bochs-cvs <bochs-cvs () lists ! sourceforge ! net>
Date: 2018-05-03 17:54:40
Message-ID: 1525370080.977407.29098 () sfp-scm-6 ! v30 ! lw ! sourceforge ! com
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Revision: 13498
Author: vruppert
Date: 2018-05-03 17:54:31 +0000 (Thu, 03 May 2018)
Log Message:
-----------
Some work on the i440BX chipset AGP support in the Bochs BIOS.
- rombios.c: return maximum bus number #1 for i440BX.
- Now using different i/o and memory base address regions for PCI and AGP.
- Added some init code for the i440BX PCI/AGP bridge.
- Some code cleanups.
Modified Paths:
--------------
trunk/bochs/bios/rombios.c
trunk/bochs/bios/rombios.h
trunk/bochs/bios/rombios32.c
Modified: trunk/bochs/bios/rombios.c
===================================================================
--- trunk/bochs/bios/rombios.c 2018-05-01 15:54:37 UTC (rev 13497)
+++ trunk/bochs/bios/rombios.c 2018-05-03 17:54:31 UTC (rev 13498)
@@ -9628,7 +9628,7 @@
cmp al, #0x01 ;; installation check
jne pci_pro_f02
mov bx, #0x0210
- mov cx, #0
+ call pci_pro_get_max_bus ;; sets CX
mov edx, #0x20494350 ;; "PCI "
mov al, #0x01
jmp pci_pro_ok
@@ -9765,6 +9765,23 @@
clc
retf
+pci_pro_get_max_bus:
+ push eax
+ mov eax, #0x80000000
+ mov dx, #0x0cf8
+ out dx, eax
+ mov dx, #0x0cfc
+ in eax, dx
+ mov cx, #0
+#ifdef PCI_FIXED_HOST_BRIDGE3
+ cmp eax, #PCI_FIXED_HOST_BRIDGE3
+ jne pci_pro_no_i440bx
+ mov cx, #0x0001
+#endif
+pci_pro_no_i440bx:
+ pop eax
+ ret
+
pci_pro_select_reg:
push edx
mov eax, #0x800000
@@ -9815,7 +9832,7 @@
jne pci_real_f02
mov ax, #0x0001
mov bx, #0x0210
- mov cx, #0
+ call pci_real_get_max_bus ;; sets CX
mov edx, #0x20494350 ;; "PCI "
mov edi, #0xf0000
mov di, #pcibios_protected
@@ -9985,6 +10002,23 @@
clc
ret
+pci_real_get_max_bus:
+ push eax
+ mov eax, #0x80000000
+ mov dx, #0x0cf8
+ out dx, eax
+ mov dx, #0x0cfc
+ in eax, dx
+ mov cx, #0
+#ifdef PCI_FIXED_HOST_BRIDGE3
+ cmp eax, #PCI_FIXED_HOST_BRIDGE3
+ jne pci_real_no_i440bx
+ mov cx, #0x0001
+#endif
+pci_real_no_i440bx:
+ pop eax
+ ret
+
pci_real_select_reg:
push dx
mov eax, #0x800000
Modified: trunk/bochs/bios/rombios.h
===================================================================
--- trunk/bochs/bios/rombios.h 2018-05-01 15:54:37 UTC (rev 13497)
+++ trunk/bochs/bios/rombios.h 2018-05-03 17:54:31 UTC (rev 13498)
@@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
-// Copyright (C) 2006 Volker Ruppert
+// Copyright (C) 2006-2018 Volker Ruppert
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@@ -250,6 +250,7 @@
#define PCI_DEVICE_ID_INTEL_82437 0x0122
#define PCI_DEVICE_ID_INTEL_82441 0x1237
#define PCI_DEVICE_ID_INTEL_82443 0x7190
+#define PCI_DEVICE_ID_INTEL_82443_1 0x7191
#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e
#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
Modified: trunk/bochs/bios/rombios32.c
===================================================================
--- trunk/bochs/bios/rombios32.c 2018-05-01 15:54:37 UTC (rev 13497)
+++ trunk/bochs/bios/rombios32.c 2018-05-03 17:54:31 UTC (rev 13498)
@@ -611,7 +611,9 @@
} PCIDevice;
static uint32_t pci_bios_io_addr;
+static uint32_t pci_bios_agp_io_addr;
static uint32_t pci_bios_mem_addr;
+static uint32_t pci_bios_agp_mem_addr;
static uint32_t pci_bios_rom_start;
/* host irqs corresponding to PCI irqs A-D */
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
@@ -756,6 +758,7 @@
{
uint16_t vendor_id, device_id;
long addr;
+ uint8_t *pir;
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
@@ -789,17 +792,32 @@
/* i440BX PCI bridge */
bios_shadow_init(d);
addr = find_pir_table();
+ pir = (uint8_t *)addr;
BX_INFO("Modify pir_table at: 0x%08lx\n", addr);
- writeb((uint8_t *)addr + 0x09, 0x38); // IRQ router DevFunc
- writeb((uint8_t *)addr + 0x1f, 0x07); // Checksum
- writeb((uint8_t *)addr + 0x21, 0x38); // 1st entry: PCI2ISA
- writeb((uint8_t *)addr + 0x31, 0x40); // 2nd entry: 1st slot
- writeb((uint8_t *)addr + 0x41, 0x48); // 3rd entry: 2nd slot
- writeb((uint8_t *)addr + 0x51, 0x50); // 4th entry: 3rd slot
- writeb((uint8_t *)addr + 0x61, 0x58); // 5th entry: 4th slot
- writeb((uint8_t *)addr + 0x70, 0x01); // 6th entry: AGP bus
- writeb((uint8_t *)addr + 0x71, 0x00); // 6th entry: AGP slot
+ writeb(pir + 0x09, 0x38); // IRQ router DevFunc
+ writeb(pir + 0x1f, 0x07); // Checksum
+ writeb(pir + 0x21, 0x38); // 1st entry: PCI2ISA
+ writeb(pir + 0x31, 0x40); // 2nd entry: 1st slot
+ writeb(pir + 0x41, 0x48); // 3rd entry: 2nd slot
+ writeb(pir + 0x51, 0x50); // 4th entry: 3rd slot
+ writeb(pir + 0x61, 0x58); // 5th entry: 4th slot
+ writeb(pir + 0x70, 0x01); // 6th entry: AGP bus
+ writeb(pir + 0x71, 0x00); // 6th entry: AGP slot
pci_config_writeb(d, 0xb4, 0x30); /* AGP aperture size 64 MB */
+ } else if (device_id == PCI_DEVICE_ID_INTEL_82443_1) {
+ /* i440BX PCI/AGP bridge */
+ pci_config_writew(d, 0x04, 0x0107);
+ pci_config_writeb(d, 0x0d, 0x40);
+ pci_config_writeb(d, 0x19, 0x01);
+ pci_config_writeb(d, 0x1a, 0x01);
+ pci_config_writeb(d, 0x1b, 0x40);
+ pci_config_writeb(d, 0x1c, 0xe0);
+ pci_config_writeb(d, 0x1d, 0xf0);
+ pci_config_writew(d, 0x20, 0xd000);
+ pci_config_writew(d, 0x22, 0xd1f0);
+ pci_config_writew(d, 0x24, 0xd200);
+ pci_config_writew(d, 0x26, 0xd3f0);
+ pci_config_writeb(d, 0xee, 0x88);
}
}
}
@@ -984,10 +1002,18 @@
if (val != 0) {
size = (~(val & ~0xf)) + 1;
if (val & PCI_ADDRESS_SPACE_IO) {
- paddr = &pci_bios_io_addr;
+ if (d->bus == 1) {
+ paddr = &pci_bios_agp_io_addr;
+ } else {
+ paddr = &pci_bios_io_addr;
+ }
align = 0x10;
} else {
- paddr = &pci_bios_mem_addr;
+ if (d->bus == 1) {
+ paddr = &pci_bios_agp_mem_addr;
+ } else {
+ paddr = &pci_bios_mem_addr;
+ }
align = 0x10000;
}
*paddr = (*paddr + size - 1) & ~(size - 1);
@@ -1059,7 +1085,9 @@
void pci_bios_init(void)
{
pci_bios_io_addr = 0xc000;
+ pci_bios_agp_io_addr = 0xe000;
pci_bios_mem_addr = 0xc0000000;
+ pci_bios_agp_mem_addr = 0xd0000000;
pci_bios_rom_start = 0xc0000;
pci_for_each_device(pci_bios_init_bridges);
------------------------------------------------------------------------------
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