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List:       bochs-cvs
Subject:    [Bochs-cvs] [13398] trunk/bochs/cpu/decoder
From:       sshwarts--- via Bochs-cvs <bochs-cvs () lists ! sourceforge ! net>
Date:       2017-12-17 17:21:02
Message-ID: 1513531262.966727.10496 () sfp-scm-5 ! v30 ! ch3 ! sourceforge ! com
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Revision: 13398
Author:   sshwarts
Date:     2017-12-17 17:21:02 +0000 (Sun, 17 Dec 2017)
Log Message:
-----------
fixup for MMX opcodes disasm

Modified Paths:
--------------
    trunk/bochs/cpu/decoder/disasm.cc
    trunk/bochs/cpu/decoder/fetchdecode.h

Modified: trunk/bochs/cpu/decoder/disasm.cc
===================================================================
--- trunk/bochs/cpu/decoder/disasm.cc	2017-12-17 16:55:10 UTC (rev 13397)
+++ trunk/bochs/cpu/decoder/disasm.cc	2017-12-17 17:21:02 UTC (rev 13398)
@@ -214,17 +214,18 @@
   else if (src_index == BX_SRC_RM) {
     switch(src_type) {
     case BX_GPR8:
-    case BX_GPR8_32:      // 8-bit  memory ref but 32-bit GPR
+    case BX_GPR32_MEM8:      // 8-bit  memory ref but 32-bit GPR
       disbufptr = dis_sprintf(disbufptr, "byte ptr ");
       break;
 
     case BX_GPR16:
-    case BX_GPR16_32:     // 16-bit memory ref but 32-bit GPR
+    case BX_GPR32_MEM16:     // 16-bit memory ref but 32-bit GPR
     case BX_SEGREG:
       disbufptr = dis_sprintf(disbufptr, "word ptr ");
       break;
 
     case BX_GPR32:
+    case BX_MMX_HALF_REG:
       disbufptr = dis_sprintf(disbufptr, "dword ptr ");
       break;
 
@@ -296,8 +297,8 @@
     break;
 
   case BX_GPR32:
-  case BX_GPR8_32:      // 8-bit  memory ref but 32-bit GPR
-  case BX_GPR16_32:     // 16-bit memory ref but 32-bit GPR
+  case BX_GPR32_MEM8:      // 8-bit  memory ref but 32-bit GPR
+  case BX_GPR32_MEM16:     // 16-bit memory ref but 32-bit GPR
     disbufptr = dis_sprintf(disbufptr, "%s", intel_general_32bit_regname[srcreg]);
     break;
 
@@ -312,6 +313,7 @@
     break;
 
   case BX_MMX_REG:
+  case BX_MMX_HALF_REG:
     disbufptr = dis_sprintf(disbufptr, "mm%d", srcreg & 0x7);
     break;
 

Modified: trunk/bochs/cpu/decoder/fetchdecode.h
===================================================================
--- trunk/bochs/cpu/decoder/fetchdecode.h	2017-12-17 16:55:10 UTC (rev 13397)
+++ trunk/bochs/cpu/decoder/fetchdecode.h	2017-12-17 17:21:02 UTC (rev 13398)
@@ -222,19 +222,20 @@
 enum {
   BX_NO_REGISTER = 0,
   BX_GPR8 = 0x1,
-  BX_GPR8_32 = 0x2,  // 8-bit memory reference but 32-bit GPR
+  BX_GPR32_MEM8 = 0x2,  // 8-bit memory reference but 32-bit GPR
   BX_GPR16 = 0x3,
-  BX_GPR16_32 = 0x4, // 16-bit memory reference but 32-bit GPR
+  BX_GPR32_MEM16 = 0x4, // 16-bit memory reference but 32-bit GPR
   BX_GPR32 = 0x5,
   BX_GPR64 = 0x6,
   BX_FPU_REG = 0x7,
   BX_MMX_REG = 0x8,
-  BX_VMM_REG = 0x9,
-  BX_KMASK_REG = 0xA,
-  BX_SEGREG = 0xB,
-  BX_CREG = 0xC,
-  BX_DREG = 0xD,
-  // encodings 0xE to 0xF are still free
+  BX_MMX_HALF_REG = 0x9,
+  BX_VMM_REG = 0xA,
+  BX_KMASK_REG = 0xB,
+  BX_SEGREG = 0xC,
+  BX_CREG = 0xD,
+  BX_DREG = 0xE,
+  // encoding 0xF still free
 };
 
 // to be used together with BX_SRC_VECTOR_RM
@@ -295,9 +296,9 @@
 const Bit8u OP_NONE = BX_SRC_NONE;
 
 const Bit8u OP_Eb = BX_FORM_SRC(BX_GPR8, BX_SRC_RM);
-const Bit8u OP_Ebd = BX_FORM_SRC(BX_GPR8_32, BX_SRC_RM);
+const Bit8u OP_Ebd = BX_FORM_SRC(BX_GPR32_MEM8, BX_SRC_RM);
 const Bit8u OP_Ew = BX_FORM_SRC(BX_GPR16, BX_SRC_RM);
-const Bit8u OP_Ewd = BX_FORM_SRC(BX_GPR16_32, BX_SRC_RM);
+const Bit8u OP_Ewd = BX_FORM_SRC(BX_GPR32_MEM16, BX_SRC_RM);
 const Bit8u OP_Ed = BX_FORM_SRC(BX_GPR32, BX_SRC_RM);
 const Bit8u OP_Eq = BX_FORM_SRC(BX_GPR64, BX_SRC_RM);
 


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