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List: bochs-cvs
Subject: [Bochs-cvs] [11784] trunk/bochs/cpu
From: sshwarts () users ! sourceforge ! net
Date: 2013-08-24 12:12:13
Message-ID: E1VDChX-0007Tq-DW () sfs-ml-3 ! v29 ! ch3 ! sourceforge ! com
[Download RAW message or body]
Revision: 11784
Author: sshwarts
Date: 2013-08-24 12:12:10 +0000 (Sat, 24 Aug 2013)
Log Message:
-----------
one more step in the way towards avx-512 which have more vector registers
Modified Paths:
--------------
trunk/bochs/cpu/debugstuff.cc
trunk/bochs/cpu/fetchdecode.cc
trunk/bochs/cpu/fetchdecode.h
trunk/bochs/cpu/fetchdecode64.cc
trunk/bochs/cpu/ia_opcodes.h
trunk/bochs/cpu/load.cc
Modified: trunk/bochs/cpu/debugstuff.cc
===================================================================
--- trunk/bochs/cpu/debugstuff.cc 2013-08-23 05:54:51 UTC (rev 11783)
+++ trunk/bochs/cpu/debugstuff.cc 2013-08-24 12:12:10 UTC (rev 11784)
@@ -147,10 +147,8 @@
else
#endif
{
- BX_INFO(("| EAX=%08x EBX=%08x ECX=%08x EDX=%08x",
- (unsigned) EAX, (unsigned) EBX, (unsigned) ECX, (unsigned) EDX));
- BX_INFO(("| ESP=%08x EBP=%08x ESI=%08x EDI=%08x",
- (unsigned) ESP, (unsigned) EBP, (unsigned) ESI, (unsigned) EDI));
+ BX_INFO(("| EAX=%08x EBX=%08x ECX=%08x EDX=%08x", EAX, EBX, ECX, EDX));
+ BX_INFO(("| ESP=%08x EBP=%08x ESI=%08x EDI=%08x", ESP, EBP, ESI, EDI));
}
BX_INFO(("| IOPL=%1u %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s",
BX_CPU_THIS_PTR get_IOPL(),
Modified: trunk/bochs/cpu/fetchdecode.cc
===================================================================
--- trunk/bochs/cpu/fetchdecode.cc 2013-08-23 05:54:51 UTC (rev 11783)
+++ trunk/bochs/cpu/fetchdecode.cc 2013-08-24 12:12:10 UTC (rev 11784)
@@ -1909,6 +1909,9 @@
case BX_SRC_RM:
i->setSrcReg(n, mod_mem ? BX_TMP_REGISTER : rm);
break;
+ case BX_SRC_VEC_RM:
+ i->setSrcReg(n, mod_mem ? BX_VECTOR_TMP_REGISTER : rm);
+ break;
#if BX_SUPPORT_AVX
case BX_SRC_MEM_NO_VVV:
if (mod_mem) break;
Modified: trunk/bochs/cpu/fetchdecode.h
===================================================================
--- trunk/bochs/cpu/fetchdecode.h 2013-08-23 05:54:51 UTC (rev 11783)
+++ trunk/bochs/cpu/fetchdecode.h 2013-08-24 12:12:10 UTC (rev 11784)
@@ -73,6 +73,7 @@
BX_SRC_EAX,
BX_SRC_NNN,
BX_SRC_RM,
+ BX_SRC_VEC_RM, // will use vector TMP register
BX_SRC_MEM_NO_VVV,
BX_SRC_VVV,
BX_SRC_VIB
Modified: trunk/bochs/cpu/fetchdecode64.cc
===================================================================
--- trunk/bochs/cpu/fetchdecode64.cc 2013-08-23 05:54:51 UTC (rev 11783)
+++ trunk/bochs/cpu/fetchdecode64.cc 2013-08-24 12:12:10 UTC (rev 11784)
@@ -2340,6 +2340,9 @@
case BX_SRC_RM:
i->setSrcReg(n, mod_mem ? BX_TMP_REGISTER : rm);
break;
+ case BX_SRC_VEC_RM:
+ i->setSrcReg(n, mod_mem ? BX_VECTOR_TMP_REGISTER : rm);
+ break;
#if BX_SUPPORT_AVX
case BX_SRC_MEM_NO_VVV:
if (mod_mem) break;
Modified: trunk/bochs/cpu/ia_opcodes.h
===================================================================
--- trunk/bochs/cpu/ia_opcodes.h 2013-08-23 05:54:51 UTC (rev 11783)
+++ trunk/bochs/cpu/ia_opcodes.h 2013-08-24 12:12:10 UTC (rev 11784)
@@ -871,10 +871,11 @@
// SSE
// SSE and SSE2
-bx_define_opcode(BX_IA_ANDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ORPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_XORPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ANDNPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_ANDPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_ORPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_XORPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_ANDNPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) +
bx_define_opcode(BX_IA_MOVUPS_VpsWps, &BX_CPU_C::MOVUPS_VpsWpsM, \
&BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVUPS_WpsVps, \
&BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_RM, \
BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVSS_VssWss, &BX_CPU_C::MOVSS_VssWssM, \
&BX_CPU_C::MOVSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) @@ -885,25 +886,25 @@
bx_define_opcode(BX_IA_MOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, \
BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVAPS_VpsWps, &BX_CPU_C::MOVAPS_VpsWpsM, \
&BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVAPS_WpsVps, \
&BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE, BX_SRC_RM, \
BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MOVNTPS_MpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, \
&BX_CPU_C::BxError, BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTPI2PS_VpsQq, &BX_CPU_C::CVTPI2PS_VpsQqM, \
&BX_CPU_C::CVTPI2PS_VpsQqR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTSI2SS_VssEd, \
&BX_CPU_C::LOAD_Ed, &BX_CPU_C::CVTSI2SS_VssEdR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MOVNTPS_MpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, \
&BX_CPU_C::BxError, BX_ISA_SSE, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTTPS2PI_PqWps, &BX_CPU_C::CVTTPS2PI_PqWps, \
&BX_CPU_C::CVTTPS2PI_PqWps, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTPS2PI_PqWps, \
&BX_CPU_C::CVTPS2PI_PqWps, &BX_CPU_C::CVTPS2PI_PqWps, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::UCOMISS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_COMISS_VpsWps, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::COMISS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_UCOMISS_VssWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_COMISS_VpsWps, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::COMISS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVMSKPS_GdVRps, \
&BX_CPU_C::BxError, &BX_CPU_C::MOVMSKPS_GdVRps, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RSQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::RSQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::RSQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RCPPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RCPPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_RCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RCPSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_RSQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::RSQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_RSQRTSS_VssWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::RSQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_RCPPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RCPPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_RCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RCPSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, \
&BX_CPU_C::PSHUFW_PqQqIb, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, \
&BX_CPU_C::PINSRW_PqEwIb, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, 0) bx_define_opcode(BX_IA_PEXTRW_GdPqIb, \
&BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdPqIb, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PMOVMSKB_GdPRq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdPRq, \
BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0) \
bx_define_opcode(BX_IA_PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, \
BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0) \
bx_define_opcode(BX_IA_PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, \
BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0) @@ \
-917,50 +918,50 @@ bx_define_opcode(BX_IA_MASKMOVQ_PqPRq, &BX_CPU_C::BxError, \
&BX_CPU_C::MASKMOVQ_PqPRq, BX_ISA_SSE | BX_ISA_3DNOW, BX_SRC_NONE, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, 0)
// SSE alias
-bx_define_opcode(BX_IA_ADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ADDSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ADDSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ADDSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ADDSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ADDSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ADDSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MULPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MULPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MULSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MULSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MULSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MULSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MULPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MULPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MULSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MULSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MULSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MULSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SUBSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SUBSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SUBSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SUBSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SUBSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SUBSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SUBSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SUBSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MINPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MINPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MINSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MINSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MINSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MINSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MINPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MINPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MINSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MINSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MINSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MINSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DIVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DIVPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DIVSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::DIVSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DIVSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::DIVSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_DIVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_DIVPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_DIVSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::DIVSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_DIVSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::DIVSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MAXPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MAXPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MAXSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MAXSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MAXSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MAXSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MAXPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPS_VpsWpsR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MAXPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPD_VpdWpdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MAXSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MAXSS_VssWssR, \
BX_ISA_SSE, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MAXSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MAXSD_VsdWsdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::SQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SQRTPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::SQRTPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::SQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SQRTSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::SQRTSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_SQRTPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPS_VpsWpsR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SQRTPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::SQRTPD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_SQRTSS_VssWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::SQRTSS_VssWssR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SQRTSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::SQRTSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CMPPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CMPPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPSS_VssWssIb, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CMPSS_VssWssIbR, BX_ISA_SSE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CMPSD_VsdWsdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CMPPS_VpsWpsIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPS_VpsWpsIbR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CMPPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CMPSS_VssWssIb, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::CMPSS_VssWssIbR, BX_ISA_SSE, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CMPSD_VsdWsdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTPS2PD_VpdWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTPD2PS_VpsWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SD_VsdWssR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTSD2SS_VssWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTPS2PD_VpdWps, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTPS2PD_VpdWpsR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTPD2PS_VpsWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTSS2SD_VsdWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SD_VsdWssR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTSD2SS_VssWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) // SSE alias
bx_define_opcode(BX_IA_MOVSD_VsdWsd, &BX_CPU_C::MOVQ_VqWqM, \
&BX_CPU_C::MOVSD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) @@ -968,19 +969,19 @@
bx_define_opcode(BX_IA_CVTPI2PD_VpdQq, &BX_CPU_C::CVTPI2PD_VpdQqM, \
&BX_CPU_C::CVTPI2PD_VpdQqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTSI2SD_VsdEd, \
&BX_CPU_C::LOAD_Ed, &BX_CPU_C::CVTSI2SD_VsdEdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTTPD2PI_PqWpd, \
&BX_CPU_C::CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTTSD2SI_GdWsd, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_CVTPD2PI_PqWpd, &BX_CPU_C::CVTPD2PI_PqWpd, \
&BX_CPU_C::CVTPD2PI_PqWpd, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_COMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::COMISD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTSD2SI_GdWsd, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_UCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_COMISD_VpdWpd, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVMSKPD_GdVRpd, &BX_CPU_C::BxError, \
&BX_CPU_C::MOVMSKPD_GdVRpd, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTDQ2PS_VpsWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKHPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKLPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTDQ2PS_VpsWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPS2DQ_VdqWpsR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_UNPCKHPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_UNPCKLPD_VpdWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PUNPCKLDQ_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVAPD_VpdWpd, &BX_CPU_C::MOVAPS_VpsWpsM, \
&BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVAPD_WpdVpd, \
&BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_RM, \
BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVDQA_VdqWdq, &BX_CPU_C::MOVAPS_VpsWpsM, \
&BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) @@ -995,87 +996,87 @@
bx_define_opcode(BX_IA_MOVNTPD_MpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, \
&BX_CPU_C::BxError, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVUPD_VpdWpd, &BX_CPU_C::MOVUPS_VpsWpsM, \
&BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVUPD_WpdVpd, \
&BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_RM, \
BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ANDNPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ANDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_XORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PAND_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PANDN_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_POR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PXOR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKLBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKLWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKLPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKSSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PACKSSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPGTB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPGTB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPGTW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPGTW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPGTD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPGTD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKUSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PACKUSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_UNPCKHPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKSSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PACKSSDW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_ANDNPD_VpdWpd, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ANDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_XORPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PAND_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PANDN_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ANDNPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_POR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PXOR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PUNPCKLBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKLBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PUNPCKLWD_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_UNPCKLPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::UNPCKLPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PACKSSWB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PCMPGTB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPGTB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PCMPGTW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PCMPGTD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPGTD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PACKUSWB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKUSWB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PUNPCKHBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PUNPCKHWD_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_UNPCKHPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::UNPCKHPS_VpsWpsR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PACKSSDW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSDW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PUNPCKHQDQ_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSHUFD_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSHUFHW_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPEQB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPEQW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPEQD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSHUFD_VdqWdqIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFD_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSHUFHW_VdqWdqIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PCMPEQB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PCMPEQW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPEQW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PCMPEQD_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, \
BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVNTI32_MdGd, &BX_CPU_C::MOV32_EdGdM, &BX_CPU_C::BxError, \
BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, 0) \
bx_define_opcode(BX_IA_PINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, \
&BX_CPU_C::PINSRW_VdqHdqEwIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_PEXTRW_GdUdqIb, \
&BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::SHUFPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::SHUFPD_VpdWpdIbR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSRLW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSRLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSRLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PADDQ_PqQq, &BX_CPU_C::PADDQ_PqQq, &BX_CPU_C::PADDQ_PqQq, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PADDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDQ_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PADDQ_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMULLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVQ_WqVq, \
&BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVDQ2Q_PqVRq, \
&BX_CPU_C::BxError, &BX_CPU_C::MOVDQ2Q_PqVRq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVQ2DQ_VdqQq, \
&BX_CPU_C::BxError, &BX_CPU_C::MOVQ2DQ_VdqQq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_PMOVMSKB_GdUdq, \
&BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdUdq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSUBUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSUBUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PADDUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PADDUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PAVGB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGB_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRAW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSRAD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PAVGW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULHUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULHUW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULHW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULHW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTDQ2PD_VpdWqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSUBSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSUBSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PADDSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PADDSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSLLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSLLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSLLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLQ_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSUBUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSUBUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSUBUSW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMINUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PADDUSB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDUSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PADDUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PADDUSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMAXUB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PAVGB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGB_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSRAW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSRAD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRAD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PAVGW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PAVGW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMULHUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULHUW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMULHW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULHW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::CVTTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTPD2DQ_VqWpd, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2DQ_VqWpdR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_CVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTDQ2PD_VpdWqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSUBSB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSUBSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMINSW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PADDSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PADDSB_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PADDSW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMAXSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXSW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSLLW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSLLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSLLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSLLQ_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PMULUDQ_PqQq, &BX_CPU_C::PMULUDQ_PqQq, \
&BX_CPU_C::PMULUDQ_PqQq, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PMULUDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULUDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMADDWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMADDWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSADBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSADBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMULUDQ_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULUDQ_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMADDWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMADDWD_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSADBW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSADBW_VdqWdqR, BX_ISA_SSE2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, \
&BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_SSE2, BX_SRC_NONE, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBB_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSUBB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBB_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PSUBQ_PqQq, &BX_CPU_C::PSUBQ_PqQq, &BX_CPU_C::PSUBQ_PqQq, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PSUBQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBQ_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDB_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSUBQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBQ_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PADDB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDB_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDW_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDD_VdqWdqR, \
BX_ISA_SSE2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PSRLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLW_UdqIb, \
BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PSRAW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAW_UdqIb, \
BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PSLLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLW_UdqIb, \
BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) @@ \
-1093,15 +1094,15 @@ // SSE and SSE2
// SSE3
-bx_define_opcode(BX_IA_MOVDDUP_VpdWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::MOVDDUP_VpdWqR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::MOVSLDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::MOVSHDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::HADDPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::HADDPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::HSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_HSUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::HSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ADDSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ADDSUBPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ADDSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_MOVDDUP_VpdWq, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MOVDDUP_VpdWqR, BX_ISA_SSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_MOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::MOVSLDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_MOVSHDUP_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MOVSHDUP_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_HADDPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::HADDPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_HADDPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HADDPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_HSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::HSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_HSUBPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ADDSUBPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ADDSUBPD_VpdWpdR, BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_ADDSUBPS_VpsWps, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDSUBPS_VpsWpsR, BX_ISA_SSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_LDDQU_VdqMdq, &BX_CPU_C::MOVUPS_VpsWpsM, &BX_CPU_C::BxError, \
BX_ISA_SSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) // \
SSE3
@@ -1124,61 +1125,61 @@
bx_define_opcode(BX_IA_PABSD_PqQq, &BX_CPU_C::PABSD_PqQq, &BX_CPU_C::PABSD_PqQq, \
BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0) \
bx_define_opcode(BX_IA_PALIGNR_PqQqIb, &BX_CPU_C::PALIGNR_PqQqIb, \
&BX_CPU_C::PALIGNR_PqQqIb, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, 0)
-bx_define_opcode(BX_IA_PSHUFB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSHUFB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHADDW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHADDD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHADDSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHADDSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMADDUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMADDUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHSUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHSUBW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHSUBD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSIGNB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSIGNB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSIGNW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSIGNW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PSIGND_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSIGND_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULHRSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULHRSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PABSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSB_VdqWdqR, \
BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PABSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSW_VdqWdqR, \
BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PABSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSD_VdqWdqR, \
BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PALIGNR_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PALIGNR_VdqWdqIbR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSHUFB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PHADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHADDW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PHADDD_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHADDD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PHADDSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHADDSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMADDUBSW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMADDUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PHSUBSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHSUBSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PHSUBW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHSUBW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PHSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHSUBD_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSIGNB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGNB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PSIGNW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PSIGNW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PSIGND_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSIGND_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMULHRSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULHRSW_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PABSB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSB_VdqWdqR, BX_ISA_SSSE3, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PABSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSW_VdqWdqR, \
BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PABSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PABSD_VdqWdqR, \
BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PALIGNR_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PALIGNR_VdqWdqIbR, BX_ISA_SSSE3, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) // SSSE3
// SSE4.1
-bx_define_opcode(BX_IA_PBLENDVB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PBLENDVB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::BLENDVPS_VpsWpsR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDVPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::BLENDVPD_VpdWpdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PTEST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PTEST_VdqWdqR, \
BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULDQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPEQQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPEQQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PACKUSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PACKUSDW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVSXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::PMOVSXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, \
&BX_CPU_C::PMOVSXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVSXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::PMOVSXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVSXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVZXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::PMOVZXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, \
&BX_CPU_C::PMOVZXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVZXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::PMOVZXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVZXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMINUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMAXUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PMULLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULLD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PHMINPOSUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ROUNDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ROUNDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDSS_VssWssIb, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::ROUNDSS_VssWssIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_ROUNDSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::ROUNDSD_VsdWsdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::BLENDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_BLENDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::BLENDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PBLENDW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PBLENDW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PBLENDVB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDVB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_BLENDVPS_VpsWps, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::BLENDVPS_VpsWpsR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_BLENDVPD_VpdWpd, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDVPD_VpdWpdR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PTEST_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PTEST_VdqWdqR, \
BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMULDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMULDQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PCMPEQQ_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PACKUSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PACKUSDW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMOVSXBW_VdqWq, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::PMOVSXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMOVSXBQ_VdqWw, \
&BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVSXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMOVSXWQ_VdqWd, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVSXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMOVZXBW_VdqWq, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::PMOVZXBD_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMOVZXBQ_VdqWw, \
&BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVZXWD_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMOVZXWQ_VdqWd, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::PMOVZXDQ_VdqWqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMINSB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMINSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMINUW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMINUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMINUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMAXSB_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSB_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMAXSD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXSD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMAXUW_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PMAXUD_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PMAXUD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PMULLD_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PHMINPOSUW_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_ROUNDPS_VpsWpsIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ROUNDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::ROUNDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_ROUNDSS_VssWssIb, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::ROUNDSS_VssWssIbR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_ROUNDSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::ROUNDSD_VsdWsdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_BLENDPS_VpsWpsIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_BLENDPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::BLENDPD_VpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PBLENDW_VdqWdqIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, \
&BX_CPU_C::PEXTRB_EbdVdqIbR, BX_ISA_SSE4_1, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_PEXTRW_EwdVdqIb, \
&BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_ISA_SSE4_1, BX_SRC_RM, \
BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, \
&BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_SSE4_1, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) @@ -1186,9 +1187,9 @@
bx_define_opcode(BX_IA_PINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqHdqEbIbM, \
&BX_CPU_C::PINSRB_VdqHdqEbIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_INSERTPS_VpsWssIb, \
&BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_SSE4_1, \
BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, \
&BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::DPPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_DPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::DPPD_VpdHpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_MPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::MPSADBW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_DPPS_VpsWpsIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DPPS_VpsWpsIbR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_DPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::DPPD_VpdHpdWpdIbR, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_MPSADBW_VdqWdqIb, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_ISA_SSE4_1, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_MOVNTDQA_VdqMdq, &BX_CPU_C::MOVAPS_VpsWpsM, \
&BX_CPU_C::BxError, BX_ISA_SSE4_1, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) // SSE4.1
@@ -1199,11 +1200,11 @@
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_CRC32_GdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CRC32_GdEqR, \
BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0) #endif
-bx_define_opcode(BX_IA_PCMPGTQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPGTQ_VdqWdqR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PCMPGTQ_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTQ_VdqWdqR, BX_ISA_SSE4_2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIb, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIb, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_ISA_SSE4_2, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) // SSE4.2
// MOVBE instruction
@@ -1239,22 +1240,22 @@
#if BX_CPU_LEVEL >= 6
// AES instructions
-bx_define_opcode(BX_IA_AESIMC_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESIMC_VdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESENC_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESENC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESENCLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESENCLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESDEC_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESDEC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESDECLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESDECLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_AESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCLMULQDQ_VdqHdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_AESIMC_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_AESENC_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESENC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_AESENCLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESENCLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_AESDEC_VdqWdq, \
&BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESDEC_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, \
BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_AESDECLAST_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESDECLAST_VdqHdqWdqR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_AESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCLMULQDQ_VdqHdqWdqIbR, BX_ISA_AES_PCLMULQDQ, BX_SRC_NNN, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_SSE)
// SHA instructions
-bx_define_opcode(BX_IA_SHA1NEXTE_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA1NEXTE_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA1MSG1_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA1MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA1MSG2_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA1MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA256RNDS2_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA256RNDS2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA256MSG1_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA256MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA256MSG2_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA256MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHA1RNDS4_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA1RNDS4_VdqWdqIbR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_SHA1NEXTE_VdqWdq, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1NEXTE_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SHA1MSG1_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA1MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_SHA1MSG2_VdqWdq, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SHA256RNDS2_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA256RNDS2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_SHA256MSG1_VdqWdq, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA256MSG1_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
+bx_define_opcode(BX_IA_SHA256MSG2_VdqWdq, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::SHA256MSG2_VdqWdqR, BX_ISA_SHA, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_SSE) +bx_define_opcode(BX_IA_SHA1RNDS4_VdqWdqIb, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::SHA1RNDS4_VdqWdqIbR, BX_ISA_SHA, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE)
#endif
@@ -1468,10 +1469,10 @@
bx_define_opcode(BX_IA_MOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, 0, \
BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_CVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, \
&BX_CPU_C::CVTSI2SS_VssEqR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, \
&BX_CPU_C::CVTSI2SD_VsdEqR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SI_GqWssR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) +bx_define_opcode(BX_IA_CVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTSD2SI_GqWsdR, 0, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_SSE) bx_define_opcode(BX_IA_MOVNTI64_MdGd, &BX_CPU_C::MOV64_EdGdM, \
&BX_CPU_C::BxError, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, 0) \
bx_define_opcode(BX_IA_MOVNTI_MqGq, &BX_CPU_C::MOV_EqGqM, &BX_CPU_C::BxError, \
BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, 0) \
bx_define_opcode(BX_IA_MOV_CR0Rq, NULL, &BX_CPU_C::MOV_CR0Rq, 0, BX_SRC_NNN, \
BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, 0) @@ -1584,10 +1585,10 @@
bx_define_opcode(BX_IA_V128_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, \
&BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_AVX) bx_define_opcode(BX_IA_V128_VMOVLPD_VpdHpdMq, \
&BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, \
BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
bx_define_opcode(BX_IA_V128_VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, \
&BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, \
BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V256_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_V256_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, \
&BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) bx_define_opcode(BX_IA_VLDDQU_VdqMdq, \
&BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX) \
bx_define_opcode(BX_IA_V128_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, \
&BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_AVX)
@@ -1599,239 +1600,239 @@
bx_define_opcode(BX_IA_V256_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, \
&BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, \
BX_PREPARE_AVX) bx_define_opcode(BX_IA_V256_VMOVNTDQ_MdqVdq, \
&BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, \
BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::COMISS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::COMISD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::VRSQRTSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VRSQRTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRCPSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::VRCPSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VRCPPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDNPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VANDNPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VHSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VHSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VADDSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VADDSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VADDSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VADDSUBPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VROUNDPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VROUNDPD_VpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::VROUNDSD_VsdHpdWsdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VROUNDSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::VROUNDSS_VssHpsWssIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VDPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VDPPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VDPPD_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::DPPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VUCOMISS_VssWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::COMISS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, \
&BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::COMISD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VRSQRTSS_VssHpsWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VRSQRTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VRCPSS_VssHpsWss, \
&BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VRCPPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VANDPS_VpsHpsWps, \
&BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VANDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VANDNPD_VpdHpdWpd, \
&BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VANDNPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VORPS_VpsHpsWps, \
&BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, \
&BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_V128_VPSHUFD_VdqWdqIb, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_V128_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_V128_VPSHUFLW_VdqWdqIb, \
&BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX) +bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, \
&BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, \
BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX) \
+bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, \
&BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, \
BX_SRC_NONE, BX_PREPARE_AVX)
@@ Diff output truncated at 98304 characters. @@
------------------------------------------------------------------------------
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