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List: bochs-cvs
Subject: [Bochs-cvs] SF.net SVN: bochs:[10522] trunk/bochs
From: sshwarts () users ! sourceforge ! net
Date: 2011-07-31 20:09:04
Message-ID: E1QncJs-0007Zb-JZ () sfp-svn-2 ! v30 ! ch3 ! sourceforge ! com
[Download RAW message or body]
Revision: 10522
http://bochs.svn.sourceforge.net/bochs/?rev=10522&view=rev
Author: sshwarts
Date: 2011-07-31 20:09:04 +0000 (Sun, 31 Jul 2011)
Log Message:
-----------
fixed *x86 ISA extensions that enable this instruction* in ia_opcodes.h
Modified Paths:
--------------
trunk/bochs/cpu/cpudb/athlon64_clawhammer.cc
trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc
trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc
trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc
trunk/bochs/cpu/cpuid.h
trunk/bochs/cpu/fetchdecode64.cc
trunk/bochs/cpu/ia_opcodes.h
trunk/bochs/disasm/disasm.h
Modified: trunk/bochs/cpu/cpudb/athlon64_clawhammer.cc
===================================================================
--- trunk/bochs/cpu/cpudb/athlon64_clawhammer.cc 2011-07-31 20:07:43 UTC (rev 10521)
+++ trunk/bochs/cpu/cpudb/athlon64_clawhammer.cc 2011-07-31 20:09:04 UTC (rev 10522)
@@ -91,6 +91,7 @@
BX_CPU_CLFLUSH |
BX_CPU_SSE |
BX_CPU_SSE2 |
+ BX_CPU_LM_LAHF_SAHF |
BX_CPU_X86_64;
}
Modified: trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc
===================================================================
--- trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc 2011-07-31 20:07:43 UTC (rev 10521)
+++ trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc 2011-07-31 20:09:04 UTC (rev 10522)
@@ -131,6 +131,7 @@
BX_CPU_VMX |
#endif
/* BX_CPU_SMX | */
+ BX_CPU_LM_LAHF_SAHF;
BX_CPU_X86_64;
}
@@ -486,7 +487,7 @@
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
// [10:0] Reserved for Intel
- // * [11:11] SYSCALL/SYSRET support
+ // ? [11:11] SYSCALL/SYSRET support
// [19:12] Reserved for Intel
// * [20:20] No-Execute page protection
// [25:21] Reserved
Modified: trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc
===================================================================
--- trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc 2011-07-31 20:07:43 UTC (rev \
10521)
+++ trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc 2011-07-31 20:09:04 UTC (rev \
10522) @@ -151,6 +151,7 @@
BX_CPU_XSAVEOPT |
BX_CPU_AES_PCLMULQDQ |
BX_CPU_AVX |
+ BX_CPU_LM_LAHF_SAHF |
BX_CPU_X86_64;
}
Modified: trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc
===================================================================
--- trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc 2011-07-31 20:07:43 UTC (rev \
10521)
+++ trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc 2011-07-31 20:09:04 UTC (rev \
10522) @@ -342,7 +342,7 @@
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
// [10:0] Reserved for Intel
- // * [11:11] SYSCALL/SYSRET support
+ // ? [11:11] SYSCALL/SYSRET support
// [19:12] Reserved for Intel
// * [20:20] No-Execute page protection
// [25:21] Reserved
Modified: trunk/bochs/cpu/cpuid.h
===================================================================
--- trunk/bochs/cpu/cpuid.h 2011-07-31 20:07:43 UTC (rev 10521)
+++ trunk/bochs/cpu/cpuid.h 2011-07-31 20:09:04 UTC (rev 10522)
@@ -82,7 +82,8 @@
#define BX_CPU_AVX_F16C (1 << 26) /* AVX F16 convert instruction */
#define BX_CPU_AVX_FMA (1 << 27) /* AVX FMA instruction */
#define BX_CPU_X86_64 (1 << 28) /* x86-64 instruction */
-#define BX_CPU_BMI (1 << 29) /* BMI instruction */
+#define BX_CPU_LM_LAHF_SAHF (1 << 29) /* Long Mode LAHF/SAHF instruction \
*/ +#define BX_CPU_BMI (1 << 30) /* BMI instruction */
// cpuid non-ISA features
#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */
Modified: trunk/bochs/cpu/fetchdecode64.cc
===================================================================
--- trunk/bochs/cpu/fetchdecode64.cc 2011-07-31 20:07:43 UTC (rev 10521)
+++ trunk/bochs/cpu/fetchdecode64.cc 2011-07-31 20:09:04 UTC (rev 10522)
@@ -297,8 +297,8 @@
/* 9B /w */ { 0, BX_IA_FWAIT },
/* 9C /w */ { 0, BX_IA_PUSHF_Fw },
/* 9D /w */ { BxTraceEnd, BX_IA_POPF_Fw },
- /* 9E /w */ { 0, BX_IA_SAHF },
- /* 9F /w */ { 0, BX_IA_LAHF },
+ /* 9E /w */ { 0, BX_IA_LM_SAHF },
+ /* 9F /w */ { 0, BX_IA_LM_LAHF },
/* A0 /w */ { BxImmediate_O, BX_IA_MOV_ALOq },
/* A1 /w */ { BxImmediate_O, BX_IA_MOV_AXOq },
/* A2 /w */ { BxImmediate_O, BX_IA_MOV_OqAL },
@@ -812,8 +812,8 @@
/* 9B /d */ { 0, BX_IA_FWAIT },
/* 9C /d */ { 0, BX_IA_PUSHF_Fq },
/* 9D /d */ { BxTraceEnd, BX_IA_POPF_Fq },
- /* 9E /d */ { 0, BX_IA_SAHF },
- /* 9F /d */ { 0, BX_IA_LAHF },
+ /* 9E /d */ { 0, BX_IA_LM_SAHF },
+ /* 9F /d */ { 0, BX_IA_LM_LAHF },
/* A0 /d */ { BxImmediate_O, BX_IA_MOV_ALOq },
/* A1 /d */ { BxImmediate_O, BX_IA_MOV_EAXOq },
/* A2 /d */ { BxImmediate_O, BX_IA_MOV_OqAL },
@@ -1327,8 +1327,8 @@
/* 9B /q */ { 0, BX_IA_FWAIT },
/* 9C /q */ { 0, BX_IA_PUSHF_Fq },
/* 9D /q */ { BxTraceEnd, BX_IA_POPF_Fq },
- /* 9E /q */ { 0, BX_IA_SAHF },
- /* 9F /q */ { 0, BX_IA_LAHF },
+ /* 9E /q */ { 0, BX_IA_LM_SAHF },
+ /* 9F /q */ { 0, BX_IA_LM_LAHF },
/* A0 /q */ { BxImmediate_O, BX_IA_MOV_ALOq },
/* A1 /q */ { BxImmediate_O, BX_IA_MOV_RAXOq },
/* A2 /q */ { BxImmediate_O, BX_IA_MOV_OqAL },
Modified: trunk/bochs/cpu/ia_opcodes.h
===================================================================
--- trunk/bochs/cpu/ia_opcodes.h 2011-07-31 20:07:43 UTC (rev 10521)
+++ trunk/bochs/cpu/ia_opcodes.h 2011-07-31 20:09:04 UTC (rev 10522)
@@ -25,7 +25,7 @@
// - Opcode name
// - Opcode execution function (/m form)
// - Opcode execution function (/r form)
-// - x86 ISA externsions that enable this instruction
+// - x86 ISA extensions that enable this instruction
// - special attributes (PREPARE_SSE, PREPARE_AVX and etc)
// in case of complex /m form instruction (load+op) /m form execution function
@@ -505,9 +505,9 @@
bx_define_opcode(BX_IA_FISTP_DWORD_INTEGER, &BX_CPU_C::FIST_DWORD_INTEGER, \
&BX_CPU_C::FIST_DWORD_INTEGER, BX_CPU_X87, 0) \
bx_define_opcode(BX_IA_FISTP_QWORD_INTEGER, &BX_CPU_C::FISTP_QWORD_INTEGER, \
&BX_CPU_C::FISTP_QWORD_INTEGER, BX_CPU_X87, 0) \
bx_define_opcode(BX_IA_FBSTP_PACKED_BCD, &BX_CPU_C::FBSTP_PACKED_BCD, \
&BX_CPU_C::FBSTP_PACKED_BCD, BX_CPU_X87, 0)
-bx_define_opcode(BX_IA_FISTTP16, &BX_CPU_C::FISTTP16, &BX_CPU_C::FISTTP16, \
BX_CPU_X87 | BX_CPU_SSE3, 0)
-bx_define_opcode(BX_IA_FISTTP32, &BX_CPU_C::FISTTP32, &BX_CPU_C::FISTTP32, \
BX_CPU_X87 | BX_CPU_SSE3, 0)
-bx_define_opcode(BX_IA_FISTTP64, &BX_CPU_C::FISTTP64, &BX_CPU_C::FISTTP64, \
BX_CPU_X87 | BX_CPU_SSE3, 0) +bx_define_opcode(BX_IA_FISTTP16, &BX_CPU_C::FISTTP16, \
&BX_CPU_C::FISTTP16, BX_CPU_SSE3, 0) +bx_define_opcode(BX_IA_FISTTP32, \
&BX_CPU_C::FISTTP32, &BX_CPU_C::FISTTP32, BX_CPU_SSE3, 0) \
+bx_define_opcode(BX_IA_FISTTP64, &BX_CPU_C::FISTTP64, &BX_CPU_C::FISTTP64, \
BX_CPU_SSE3, 0) bx_define_opcode(BX_IA_FNINIT, &BX_CPU_C::FNINIT, &BX_CPU_C::FNINIT, \
BX_CPU_X87, 0) bx_define_opcode(BX_IA_FNCLEX, &BX_CPU_C::FNCLEX, &BX_CPU_C::FNCLEX, \
BX_CPU_X87, 0) bx_define_opcode(BX_IA_FRSTOR, &BX_CPU_C::FRSTOR, &BX_CPU_C::FRSTOR, \
BX_CPU_X87, 0) @@ -565,10 +565,10 @@
bx_define_opcode(BX_IA_FCOMP_STi, &BX_CPU_C::FCOM_STi, &BX_CPU_C::FCOM_STi, \
BX_CPU_X87, 0) bx_define_opcode(BX_IA_FUCOM_STi, &BX_CPU_C::FUCOM_STi, \
&BX_CPU_C::FUCOM_STi, BX_CPU_X87, 0) bx_define_opcode(BX_IA_FUCOMP_STi, \
&BX_CPU_C::FUCOM_STi, &BX_CPU_C::FUCOM_STi, BX_CPU_X87, 0)
-bx_define_opcode(BX_IA_FCOMI_ST0_STj, &BX_CPU_C::FCOMI_ST0_STj, \
&BX_CPU_C::FCOMI_ST0_STj, BX_CPU_X87 | BX_CPU_P6, 0)
-bx_define_opcode(BX_IA_FCOMIP_ST0_STj, &BX_CPU_C::FCOMI_ST0_STj, \
&BX_CPU_C::FCOMI_ST0_STj, BX_CPU_X87 | BX_CPU_P6, 0)
-bx_define_opcode(BX_IA_FUCOMI_ST0_STj, &BX_CPU_C::FUCOMI_ST0_STj, \
&BX_CPU_C::FUCOMI_ST0_STj, BX_CPU_X87 | BX_CPU_P6, 0)
-bx_define_opcode(BX_IA_FUCOMIP_ST0_STj, &BX_CPU_C::FUCOMI_ST0_STj, \
&BX_CPU_C::FUCOMI_ST0_STj, BX_CPU_X87 | BX_CPU_P6, 0) \
+bx_define_opcode(BX_IA_FCOMI_ST0_STj, &BX_CPU_C::FCOMI_ST0_STj, \
&BX_CPU_C::FCOMI_ST0_STj, BX_CPU_P6, 0) +bx_define_opcode(BX_IA_FCOMIP_ST0_STj, \
&BX_CPU_C::FCOMI_ST0_STj, &BX_CPU_C::FCOMI_ST0_STj, BX_CPU_P6, 0) \
+bx_define_opcode(BX_IA_FUCOMI_ST0_STj, &BX_CPU_C::FUCOMI_ST0_STj, \
&BX_CPU_C::FUCOMI_ST0_STj, BX_CPU_P6, 0) +bx_define_opcode(BX_IA_FUCOMIP_ST0_STj, \
&BX_CPU_C::FUCOMI_ST0_STj, &BX_CPU_C::FUCOMI_ST0_STj, BX_CPU_P6, 0) \
bx_define_opcode(BX_IA_FCOM_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, \
&BX_CPU_C::FCOM_SINGLE_REAL, BX_CPU_X87, 0) \
bx_define_opcode(BX_IA_FCOMP_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, \
&BX_CPU_C::FCOM_SINGLE_REAL, BX_CPU_X87, 0) bx_define_opcode(BX_IA_FCOM_DOUBLE_REAL, \
&BX_CPU_C::FCOM_DOUBLE_REAL, &BX_CPU_C::FCOM_DOUBLE_REAL, BX_CPU_X87, 0) @@ -577,7 \
+577,7 @@ bx_define_opcode(BX_IA_FICOMP_WORD_INTEGER, &BX_CPU_C::FICOM_WORD_INTEGER, \
&BX_CPU_C::FICOM_WORD_INTEGER, BX_CPU_X87, 0) \
bx_define_opcode(BX_IA_FICOM_DWORD_INTEGER, &BX_CPU_C::FICOM_DWORD_INTEGER, \
&BX_CPU_C::FICOM_DWORD_INTEGER, BX_CPU_X87, 0) \
bx_define_opcode(BX_IA_FICOMP_DWORD_INTEGER, &BX_CPU_C::FICOM_DWORD_INTEGER, \
&BX_CPU_C::FICOM_DWORD_INTEGER, BX_CPU_X87, 0)
-bx_define_opcode(BX_IA_FCMOV_ST0_STj, &BX_CPU_C::FCMOV_ST0_STj, \
&BX_CPU_C::FCMOV_ST0_STj, BX_CPU_X87 | BX_CPU_P6, 0) \
+bx_define_opcode(BX_IA_FCMOV_ST0_STj, &BX_CPU_C::FCMOV_ST0_STj, \
&BX_CPU_C::FCMOV_ST0_STj, BX_CPU_P6, 0) bx_define_opcode(BX_IA_FCOMPP, \
&BX_CPU_C::FCOMPP, &BX_CPU_C::FCOMPP, BX_CPU_X87, 0) bx_define_opcode(BX_IA_FUCOMPP, \
&BX_CPU_C::FUCOMPP, &BX_CPU_C::FUCOMPP, BX_CPU_X87, 0) \
bx_define_opcode(BX_IA_FXCH_STi, &BX_CPU_C::FXCH_STi, &BX_CPU_C::FXCH_STi, \
BX_CPU_X87, 0) @@ -690,7 +690,7 @@
bx_define_opcode(BX_IA_PSRLQ_PqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLQ_PqIb, \
BX_CPU_MMX, 0) bx_define_opcode(BX_IA_PSLLQ_PqIb, &BX_CPU_C::BxError, \
&BX_CPU_C::PSLLQ_PqIb, BX_CPU_MMX, 0) #if BX_SUPPORT_X86_64
-bx_define_opcode(BX_IA_MOVQ_EqPq, &BX_CPU_C::MOVQ_QqPqM, &BX_CPU_C::MOVQ_EqPqR, \
BX_CPU_MMX | BX_CPU_X86_64, 0) +bx_define_opcode(BX_IA_MOVQ_EqPq, \
&BX_CPU_C::MOVQ_QqPqM, &BX_CPU_C::MOVQ_EqPqR, BX_CPU_X86_64, 0) #endif
// MMX
@@ -1088,7 +1088,7 @@
bx_define_opcode(BX_IA_CRC32_GdEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::CRC32_GdEwR, \
BX_CPU_SSE4_2, 0) bx_define_opcode(BX_IA_CRC32_GdEd, &BX_CPU_C::LOAD_Ed, \
&BX_CPU_C::CRC32_GdEdR, BX_CPU_SSE4_2, 0) #if BX_SUPPORT_X86_64
-bx_define_opcode(BX_IA_CRC32_GdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CRC32_GdEqR, \
BX_CPU_SSE4_2 | BX_CPU_X86_64, 0) +bx_define_opcode(BX_IA_CRC32_GdEq, \
&BX_CPU_C::LOAD_Eq, &BX_CPU_C::CRC32_GdEqR, BX_CPU_SSE4_2, 0) #endif
bx_define_opcode(BX_IA_PCMPGTQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, \
&BX_CPU_C::PCMPGTQ_VdqWdqR, BX_CPU_SSE4_2, BX_PREPARE_SSE) \
bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, \
&BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE) @@ -1101,12 +1101,12 \
@@ bx_define_opcode(BX_IA_MOVBE_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::MOVBE_GwEwR, \
BX_CPU_MOVBE, 0) bx_define_opcode(BX_IA_MOVBE_GdEd, &BX_CPU_C::LOAD_Ed, \
&BX_CPU_C::MOVBE_GdEdR, BX_CPU_MOVBE, 0) #if BX_SUPPORT_X86_64
-bx_define_opcode(BX_IA_MOVBE_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::MOVBE_GqEqR, \
BX_CPU_MOVBE | BX_CPU_X86_64, 0) +bx_define_opcode(BX_IA_MOVBE_GqEq, \
&BX_CPU_C::LOAD_Eq, &BX_CPU_C::MOVBE_GqEqR, BX_CPU_MOVBE, 0) #endif
bx_define_opcode(BX_IA_MOVBE_EwGw, &BX_CPU_C::MOVBE_EwGw, &BX_CPU_C::MOVBE_EwGw, \
BX_CPU_MOVBE, 0) bx_define_opcode(BX_IA_MOVBE_EdGd, &BX_CPU_C::MOVBE_EdGd, \
&BX_CPU_C::MOVBE_EdGd, BX_CPU_MOVBE, 0) #if BX_SUPPORT_X86_64
-bx_define_opcode(BX_IA_MOVBE_EqGq, &BX_CPU_C::MOVBE_EqGq, &BX_CPU_C::MOVBE_EqGq, \
BX_CPU_MOVBE | BX_CPU_X86_64, 0) +bx_define_opcode(BX_IA_MOVBE_EqGq, \
&BX_CPU_C::MOVBE_EqGq, &BX_CPU_C::MOVBE_EqGq, BX_CPU_MOVBE, 0) #endif
// MOVBE instruction
@@ -1116,7 +1116,7 @@
bx_define_opcode(BX_IA_POPCNT_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::POPCNT_GdEdR, \
BX_CPU_SSE4_2, 0) bx_define_opcode(BX_IA_POPCNT_GwEw, &BX_CPU_C::LOAD_Ew, \
&BX_CPU_C::POPCNT_GwEwR, BX_CPU_SSE4_2, 0) #if BX_SUPPORT_X86_64
-bx_define_opcode(BX_IA_POPCNT_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::POPCNT_GqEqR, \
BX_CPU_SSE4_2 | BX_CPU_X86_64, 0) +bx_define_opcode(BX_IA_POPCNT_GqEq, \
&BX_CPU_C::LOAD_Eq, &BX_CPU_C::POPCNT_GqEqR, BX_CPU_SSE4_2, 0) #endif
// POPCNT instruction
@@ -1141,6 +1141,9 @@
#endif
#if BX_SUPPORT_X86_64
+bx_define_opcode(BX_IA_LM_LAHF, NULL, &BX_CPU_C::LAHF, BX_CPU_LM_LAHF_SAHF, 0)
+bx_define_opcode(BX_IA_LM_SAHF, NULL, &BX_CPU_C::SAHF, BX_CPU_LM_LAHF_SAHF, 0)
+
bx_define_opcode(BX_IA_ADD_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADD_GqEqR, \
BX_CPU_X86_64, 0) bx_define_opcode(BX_IA_OR_GqEq, &BX_CPU_C::LOAD_Eq, \
&BX_CPU_C::OR_GqEqR, BX_CPU_X86_64, 0) bx_define_opcode(BX_IA_ADC_GqEq, \
&BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADC_GqEqR, BX_CPU_X86_64, 0) @@ -1328,10 +1331,10 @@
bx_define_opcode(BX_IA_MOV_DqRq, NULL, &BX_CPU_C::MOV_DqRq, BX_CPU_X86_64, 0)
bx_define_opcode(BX_IA_MOV_RqDq, NULL, &BX_CPU_C::MOV_RqDq, BX_CPU_X86_64, 0)
bx_define_opcode(BX_IA_SWAPGS, &BX_CPU_C::BxError, &BX_CPU_C::SWAPGS, BX_CPU_X86_64, \
0)
-bx_define_opcode(BX_IA_RDFSBASE, &BX_CPU_C::BxError, &BX_CPU_C::RDFSBASE, \
BX_CPU_X86_64 | BX_CPU_FSGSBASE, 0)
-bx_define_opcode(BX_IA_RDGSBASE, &BX_CPU_C::BxError, &BX_CPU_C::RDGSBASE, \
BX_CPU_X86_64 | BX_CPU_FSGSBASE, 0)
-bx_define_opcode(BX_IA_WRFSBASE, &BX_CPU_C::BxError, &BX_CPU_C::WRFSBASE, \
BX_CPU_X86_64 | BX_CPU_FSGSBASE, 0)
-bx_define_opcode(BX_IA_WRGSBASE, &BX_CPU_C::BxError, &BX_CPU_C::WRGSBASE, \
BX_CPU_X86_64 | BX_CPU_FSGSBASE, 0) +bx_define_opcode(BX_IA_RDFSBASE, \
&BX_CPU_C::BxError, &BX_CPU_C::RDFSBASE, BX_CPU_FSGSBASE, 0) \
+bx_define_opcode(BX_IA_RDGSBASE, &BX_CPU_C::BxError, &BX_CPU_C::RDGSBASE, \
BX_CPU_FSGSBASE, 0) +bx_define_opcode(BX_IA_WRFSBASE, &BX_CPU_C::BxError, \
&BX_CPU_C::WRFSBASE, BX_CPU_FSGSBASE, 0) +bx_define_opcode(BX_IA_WRGSBASE, \
&BX_CPU_C::BxError, &BX_CPU_C::WRGSBASE, BX_CPU_FSGSBASE, 0) #endif
bx_define_opcode(BX_IA_RDTSCP, &BX_CPU_C::BxError, &BX_CPU_C::RDTSCP, BX_CPU_RDTSCP, \
0) @@ -1348,12 +1351,12 @@
bx_define_opcode(BX_IA_VMREAD_EdGd, &BX_CPU_C::VMREAD, &BX_CPU_C::VMREAD, \
BX_CPU_VMX, 0) bx_define_opcode(BX_IA_VMWRITE_GdEd, &BX_CPU_C::VMWRITE, \
&BX_CPU_C::VMWRITE, BX_CPU_VMX, 0) #if BX_SUPPORT_X86_64
-bx_define_opcode(BX_IA_VMREAD_EqGq, &BX_CPU_C::VMREAD, &BX_CPU_C::VMREAD, \
BX_CPU_X86_64 | BX_CPU_VMX, 0)
-bx_define_opcode(BX_IA_VMWRITE_GqEq, &BX_CPU_C::VMWRITE, &BX_CPU_C::VMWRITE, \
BX_CPU_X86_64 | BX_CPU_VMX, 0) +bx_define_opcode(BX_IA_VMREAD_EqGq, \
&BX_CPU_C::VMREAD, &BX_CPU_C::VMREAD, BX_CPU_VMX, 0) \
+bx_define_opcode(BX_IA_VMWRITE_GqEq, &BX_CPU_C::VMWRITE, &BX_CPU_C::VMWRITE, \
BX_CPU_VMX, 0) #endif
#if BX_CPU_LEVEL >= 6
-bx_define_opcode(BX_IA_INVEPT, &BX_CPU_C::INVEPT, &BX_CPU_C::BxError, BX_CPU_X86_64 \
| BX_CPU_VMX, 0)
-bx_define_opcode(BX_IA_INVVPID, &BX_CPU_C::INVVPID, &BX_CPU_C::BxError, \
BX_CPU_X86_64 | BX_CPU_VMX, 0) +bx_define_opcode(BX_IA_INVEPT, &BX_CPU_C::INVEPT, \
&BX_CPU_C::BxError, BX_CPU_VMX, 0) +bx_define_opcode(BX_IA_INVVPID, \
&BX_CPU_C::INVVPID, &BX_CPU_C::BxError, BX_CPU_VMX, 0) #endif
// VMX
@@ -1644,16 +1647,16 @@
bx_define_opcode(BX_IA_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 \
| BX_VEX_L256) bx_define_opcode(BX_IA_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTTSD2SI_GdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 \
| BX_VEX_L256) bx_define_opcode(BX_IA_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 \
| BX_VEX_L256)
-bx_define_opcode(BX_IA_VCVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, \
&BX_CPU_C::VCVTSI2SD_VsdEqR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128 \
| BX_VEX_L256)
-bx_define_opcode(BX_IA_VCVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, \
&BX_CPU_C::VCVTSI2SS_VssEqR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128 \
| BX_VEX_L256)
-bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTTSD2SI_GqWsdR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | \
BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
-bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTTSS2SI_GqWssR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | \
BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
-bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTSD2SI_GqWsdR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | \
BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
-bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SI_GqWssR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | \
BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
-bx_define_opcode(BX_IA_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, \
&BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | \
BX_VEX_NO_VVV | BX_VEX_L128)
-bx_define_opcode(BX_IA_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqEdIbM, \
&BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX | BX_CPU_X86_64, \
BX_PREPARE_AVX | BX_VEX_L128)
-bx_define_opcode(BX_IA_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, \
BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128)
-bx_define_opcode(BX_IA_VMOVQ_EqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_EqVqR, \
BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128) \
+bx_define_opcode(BX_IA_VCVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, \
&BX_CPU_C::VCVTSI2SD_VsdEqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256) \
+bx_define_opcode(BX_IA_VCVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, \
&BX_CPU_C::VCVTSI2SS_VssEqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256) \
+bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTTSD2SI_GqWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 \
| BX_VEX_L256) +bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTTSS2SI_GqWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 \
| BX_VEX_L256) +bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, \
&BX_CPU_C::CVTSD2SI_GqWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 \
| BX_VEX_L256) +bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, \
&BX_CPU_C::CVTSS2SI_GqWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 \
| BX_VEX_L256) +bx_define_opcode(BX_IA_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, \
&BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128) \
+bx_define_opcode(BX_IA_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqEdIbM, \
&BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) \
+bx_define_opcode(BX_IA_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, \
BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) +bx_define_opcode(BX_IA_VMOVQ_EqVq, \
&BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_EqVqR, BX_CPU_AVX, BX_PREPARE_AVX | \
BX_VEX_L128)
bx_define_opcode(BX_IA_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_VectorQ, \
&BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_CPU_AVX_F16C, BX_PREPARE_AVX | BX_VEX_NO_VVV | \
BX_VEX_L128 | BX_VEX_L256) bx_define_opcode(BX_IA_VCVTPS2PH_WpsVpsIb, \
&BX_CPU_C::VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, BX_CPU_AVX_F16C, \
BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
Modified: trunk/bochs/disasm/disasm.h
===================================================================
--- trunk/bochs/disasm/disasm.h 2011-07-31 20:07:43 UTC (rev 10521)
+++ trunk/bochs/disasm/disasm.h 2011-07-31 20:09:04 UTC (rev 10522)
@@ -68,7 +68,8 @@
#define IA_AVX_F16C (1 << 26) /* AVX F16 convert instruction */
#define IA_AVX_FMA (1 << 27) /* AVX FMA instruction */
#define IA_X86_64 (1 << 28) /* x86-64 instruction */
-#define IA_BMI (1 << 29) /* BMI instruction */
+#define IA_LM_LAHF_SAHF (1 << 29) /* Long Mode LAHF/SAHF instruction */
+#define IA_BMI (1 << 30) /* BMI instruction */
/* general purpose bit register */
enum {
This was sent by the SourceForge.net collaborative development platform, the world's \
largest Open Source development site.
------------------------------------------------------------------------------
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