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List: bochs-cvs
Subject: [Bochs-cvs] SF.net SVN: bochs:[10505] trunk/bochs
From: sshwarts () users ! sourceforge ! net
Date: 2011-07-29 15:03:55
Message-ID: E1QmobT-0007Mq-EO () sfp-svn-5 ! v30 ! ch3 ! sourceforge ! com
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Revision: 10505
http://bochs.svn.sourceforge.net/bochs/?rev=10505&view=rev
Author: sshwarts
Date: 2011-07-29 15:03:54 +0000 (Fri, 29 Jul 2011)
Log Message:
-----------
Added several predefined CPUs that can be selected from .bochsrc using new CPU::MODEL \
option. Selecting CPU MODEL from .bochsrc automatically chooses real HW CPUID and \
also configures Bochs emulator to emulate this specific CPU including all its \
features only. Supported CPUs to choose from:
core2_extreme_x9770
corei7_sandy_bridge_2600K
p4_prescott_celeron_336
Modified Paths:
--------------
trunk/bochs/.bochsrc
trunk/bochs/CHANGES
trunk/bochs/PARAM_TREE.txt
trunk/bochs/config.cc
trunk/bochs/cpu/Makefile.in
trunk/bochs/cpu/cpuid.h
trunk/bochs/cpu/init.cc
trunk/bochs/gui/siminterface.h
trunk/bochs/param_names.h
Added Paths:
-----------
trunk/bochs/cpu/cpudb/
trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc
trunk/bochs/cpu/cpudb/core2_extreme_x9770.h
trunk/bochs/cpu/cpudb/core2_extreme_x9770.txt
trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc
trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.h
trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.txt
trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc
trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.h
trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.txt
Modified: trunk/bochs/.bochsrc
===================================================================
--- trunk/bochs/.bochsrc 2011-07-29 08:16:28 UTC (rev 10504)
+++ trunk/bochs/.bochsrc 2011-07-29 15:03:54 UTC (rev 10505)
@@ -85,43 +85,53 @@
# CPU:
# This defines cpu-related parameters inside Bochs:
#
+# MODEL:
+# Selects CPU configuration to emulate from pre-defined list of all
+# supported configurations. When this option is used, the CPUID option
+# has no effect anymore.
+#
+# CPU configurations that can be selected:
+# ------------------------------------------------------
+# core2_pnr Intel(R) Core(TM)2 Extreme CPU X9770
+# core2_snb Intel(R) Core(TM) i7-2600K CPU
+#
# COUNT:
-# Set the number of processors:cores per processor:threads per core
-# when Bochs is compiled for SMP emulation.
-# Bochs currently supports up to 8 threads running simultaniosly.
-# If Bochs is compiled without SMP support, it won't accept values
-# different from 1.
+# Set the number of processors:cores per processor:threads per core
+# when Bochs is compiled for SMP emulation.
+# Bochs currently supports up to 8 threads running simultaniosly.
+# If Bochs is compiled without SMP support, it won't accept values
+# different from 1.
#
# QUANTUM:
-# Maximum amount of instructions allowed to execute by processor before
-# returning control to another cpu. This option exists only in Bochs
-# binary compiled with SMP support.
+# Maximum amount of instructions allowed to execute by processor before
+# returning control to another cpu. This option exists only in Bochs
+# binary compiled with SMP support.
#
# RESET_ON_TRIPLE_FAULT:
-# Reset the CPU when triple fault occur (highly recommended) rather than
-# PANIC. Remember that if you trying to continue after triple fault the
-# simulation will be completely bogus !
+# Reset the CPU when triple fault occur (highly recommended) rather than
+# PANIC. Remember that if you trying to continue after triple fault the
+# simulation will be completely bogus !
#
# MSRS:
-# Define path to user CPU Model Specific Registers (MSRs) specification.
-# See example in msrs.def.
+# Define path to user CPU Model Specific Registers (MSRs) specification.
+# See example in msrs.def.
#
# IGNORE_BAD_MSRS:
-# Ignore MSR references that Bochs does not understand; print a warning
-# message instead of generating #GP exception. This option is enabled
-# by default but will not be avaiable if configurable MSRs are enabled.
+# Ignore MSR references that Bochs does not understand; print a warning
+# message instead of generating #GP exception. This option is enabled
+# by default but will not be avaiable if configurable MSRs are enabled.
#
# IPS:
-# Emulated Instructions Per Second. This is the number of IPS that bochs
-# is capable of running on your machine. You can recompile Bochs with
-# --enable-show-ips option enabled, to find your host's capability.
-# Measured IPS value will then be logged into your log file or shown
-# in the status bar (if supported by the gui).
+# Emulated Instructions Per Second. This is the number of IPS that bochs
+# is capable of running on your machine. You can recompile Bochs with
+# --enable-show-ips option enabled, to find your host's capability.
+# Measured IPS value will then be logged into your log file or shown
+# in the status bar (if supported by the gui).
#
-# IPS is used to calibrate many time-dependent events within the bochs
-# simulation. For example, changing IPS affects the frequency of VGA
-# updates, the duration of time before a key starts to autorepeat, and
-# the measurement of BogoMips and other benchmarks.
+# IPS is used to calibrate many time-dependent events within the bochs
+# simulation. For example, changing IPS affects the frequency of VGA
+# updates, the duration of time before a key starts to autorepeat, and
+# the measurement of BogoMips and other benchmarks.
#
# Examples:
#
@@ -138,94 +148,95 @@
#=======================================================================
# CPUID:
#
-# This defines features and functionality supported by Bochs emulated CPU:
+# This defines features and functionality supported by Bochs emulated CPU.
+# The option has no offect if CPU model was selected in CPU option.
#
# MMX:
-# Select MMX instruction set support.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 5.
+# Select MMX instruction set support.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 5.
#
# APIC:
-# Select APIC configuration (LEGACY/XAPIC/X2APIC).
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 5.
+# Select APIC configuration (LEGACY/XAPIC/X2APIC).
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 5.
#
# SEP:
-# Select SYSENTER/SYSEXIT instruction set support.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+# Select SYSENTER/SYSEXIT instruction set support.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# SSE:
-# Select SSE instruction set support.
-# Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+# Select SSE instruction set support.
+# Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# AES:
-# Select AES instruction set support.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+# Select AES instruction set support.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# MOVBE:
-# Select MOVBE Intel(R) Atom instruction support.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+# Select MOVBE Intel(R) Atom instruction support.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# XSAVE:
-# Select XSAVE extensions support.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+# Select XSAVE extensions support.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# XSAVEOPT:
-# Select XSAVEOPT instruction support.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+# Select XSAVEOPT instruction support.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# AVX:
-# Select AVX instruction set support.
-# This option exists only if Bochs compiled with --enable-avx option.
+# Select AVX instruction set support.
+# This option exists only if Bochs compiled with --enable-avx option.
#
# AVX_F16C:
-# Select AVX float16 convert instructions support.
-# This option exists only if Bochs compiled with --enable-avx option.
+# Select AVX float16 convert instructions support.
+# This option exists only if Bochs compiled with --enable-avx option.
#
# 1G_PAGES:
-# Enable 1G page size support in long mode.
-# This option exists only if Bochs compiled with x86-64 support.
+# Enable 1G page size support in long mode.
+# This option exists only if Bochs compiled with x86-64 support.
#
# PCID:
-# Enable Process-Context Identifiers (PCID) support in long mode.
-# This option exists only if Bochs compiled with x86-64 support.
+# Enable Process-Context Identifiers (PCID) support in long mode.
+# This option exists only if Bochs compiled with x86-64 support.
#
# FSGSBASE:
-# Enable GS/GS BASE access instructions support in long mode.
-# This option exists only if Bochs compiled with x86-64 support.
+# Enable GS/GS BASE access instructions support in long mode.
+# This option exists only if Bochs compiled with x86-64 support.
#
# SMEP:
-# Enable Supervisor Mode Execution Protection (SMEP) support.
-# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+# Enable Supervisor Mode Execution Protection (SMEP) support.
+# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# MWAIT:
-# Select MONITOR/MWAIT instructions support.
-# This option exists only if Bochs compiled with --enable-monitor-mwait.
+# Select MONITOR/MWAIT instructions support.
+# This option exists only if Bochs compiled with --enable-monitor-mwait.
#
# MWAIT_IS_NOP:
-# When this option is enabled MWAIT will not put the CPU into a sleep state.
-# This option exists only if Bochs compiled with --enable-monitor-mwait.
+# When this option is enabled MWAIT will not put the CPU into a sleep state.
+# This option exists only if Bochs compiled with --enable-monitor-mwait.
#
# VENDOR_STRING:
-# Set the CPUID vendor string returned by CPUID(0x0). This should be a
-# twelve-character ASCII string.
+# Set the CPUID vendor string returned by CPUID(0x0). This should be a
+# twelve-character ASCII string.
#
# BRAND_STRING:
-# Set the CPUID vendor string returned by CPUID(0x80000002 .. 0x80000004).
-# This should be at most a forty-eight-character ASCII string.
+# Set the CPUID vendor string returned by CPUID(0x80000002 .. 0x80000004).
+# This should be at most a forty-eight-character ASCII string.
#
# FAMILY:
-# Set model information returned by CPUID. Default family value determined
-# by configure option --enable-cpu-level.
+# Set model information returned by CPUID. Default family value determined
+# by configure option --enable-cpu-level.
#
# MODEL:
-# Set model information returned by CPUID. Default model value is 3.
+# Set model information returned by CPUID. Default model value is 3.
#
# STEPPING:
-# Set stepping information returned by CPUID. Default stepping value is 3.
+# Set stepping information returned by CPUID. Default stepping value is 3.
#
# CPUID_LIMIT_WINNT:
-# Determine whether to limit maximum CPUID function to 3. This mode is
-# required to workaround WinNT installation and boot issues.
+# Determine whether to limit maximum CPUID function to 3. This mode is
+# required to workaround WinNT installation and boot issues.
#=======================================================================
cpuid: mmx=1, sep=1, sse=sse4_2, apic=xapic, aes=1, movbe=1, xsave=1
cpuid: family=6, model=0x1a, stepping=5
Modified: trunk/bochs/CHANGES
===================================================================
--- trunk/bochs/CHANGES 2011-07-29 08:16:28 UTC (rev 10504)
+++ trunk/bochs/CHANGES 2011-07-29 15:03:54 UTC (rev 10505)
@@ -101,6 +101,7 @@
[3190995] add eth backend based on Slirp by Heikki Lindholm
- these S.F. bugs were closed/fixed
+ [3277639] incompatible colours in palette
[1788739] Abort on large memory setting
[3012207] Int 13h FN 48h incorrect return values
[3363289] holding shift key causes capslock hang
Modified: trunk/bochs/PARAM_TREE.txt
===================================================================
--- trunk/bochs/PARAM_TREE.txt 2011-07-29 08:16:28 UTC (rev 10504)
+++ trunk/bochs/PARAM_TREE.txt 2011-07-29 15:03:54 UTC (rev 10505)
@@ -20,13 +20,14 @@
n_processors
n_cores
n_threads
+ model
ips
quantum
reset_on_triple_fault
msrs
+ cpuid_limit_winnt
cpuid
- cpuid_limit_winnt
family
model
stepping
Modified: trunk/bochs/config.cc
===================================================================
--- trunk/bochs/config.cc 2011-07-29 08:16:28 UTC (rev 10504)
+++ trunk/bochs/config.cc 2011-07-29 15:03:54 UTC (rev 10505)
@@ -217,23 +217,42 @@
#endif
// cpu subtree
- bx_list_c *cpu_param = new bx_list_c(root_param, "cpu", "CPU Options", 8 + \
BX_SUPPORT_SMP); + bx_list_c *cpu_param = new bx_list_c(root_param, "cpu", "CPU \
Options", 10 + BX_SUPPORT_SMP);
+ static const char *cpu_names[] = {
+ "bochs",
+#if BX_SUPPORT_X86_64
+ "p4_prescott_celeron_336",
+ "core2_extreme_x9770",
+#if BX_SUPPORT_AVX
+ "corei7_sandy_bridge_2600k",
+#endif
+#endif
+ NULL
+ };
+
+ new bx_param_enum_c(cpu_param,
+ "model", "CPU configuration",
+ "Choose pre-defined CPU configuration",
+ cpu_names,
+ BX_CPU_MODEL_BOCHS,
+ BX_CPU_MODEL_BOCHS);
+
// cpu options
bx_param_num_c *nprocessors = new bx_param_num_c(cpu_param,
- "n_processors", "Number of CPUs in SMP mode",
- "Sets the number of CPUs for multiprocessor emulation",
+ "n_processors", "Number of processors in SMP mode",
+ "Sets the number of processors for multiprocessor emulation",
1, BX_CPU_PROCESSORS_LIMIT,
1);
nprocessors->set_enabled(BX_CPU_PROCESSORS_LIMIT > 1);
bx_param_num_c *ncores = new bx_param_num_c(cpu_param,
- "n_cores", "Number of processor cores in each CPU in SMP mode",
- "Sets the number of processor cores per CPU for multiprocessor emulation",
+ "n_cores", "Number of cores in each processor in SMP mode",
+ "Sets the number of cores per processor for multiprocessor emulation",
1, BX_CPU_CORES_LIMIT,
1);
ncores->set_enabled(BX_CPU_CORES_LIMIT > 1);
bx_param_num_c *nthreads = new bx_param_num_c(cpu_param,
- "n_threads", "Number of HT threads per each process core in SMP mode",
+ "n_threads", "Number of HT threads per each core in SMP mode",
"Sets the number of HT (Intel(R) HyperThreading Technology) threads per core \
for multiprocessor emulation", 1, BX_CPU_HT_THREADS_LIMIT,
1);
@@ -256,10 +275,14 @@
1);
#if BX_CPU_LEVEL >= 5
new bx_param_bool_c(cpu_param,
- "ignore_bad_msrs", "Ignore RDMSR/WRMSR to unknown MSR register",
+ "ignore_bad_msrs", "Ignore RDMSR / WRMSR to unknown MSR register",
"Ignore RDMSR/WRMSR to unknown MSR register",
1);
#endif
+ new bx_param_bool_c(cpu_param,
+ "cpuid_limit_winnt", "Limit max CPUID function to 3",
+ "Limit max CPUID function reported to 3 to workaround WinNT issue",
+ 0);
#if BX_CONFIGURE_MSRS
new bx_param_filename_c(cpu_param,
"msrs",
@@ -272,13 +295,8 @@
// cpuid subtree
#if BX_CPU_LEVEL >= 4
- bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 22);
+ bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 21);
- new bx_param_bool_c(cpuid_param,
- "cpuid_limit_winnt", "Limit max CPUID function to 3",
- "Limit max CPUID function reported to 3 to workaround WinNT issue",
- 0);
-
new bx_param_string_c(cpuid_param,
"vendor_string",
"CPUID vendor string",
@@ -2601,6 +2619,9 @@
SIM->get_param_num(BXPN_CPU_NPROCESSORS)->set(processors);
SIM->get_param_num(BXPN_CPU_NCORES)->set(cores);
SIM->get_param_num(BXPN_CPU_NTHREADS)->set(threads);
+ } else if (!strncmp(params[i], "model=", 6)) {
+ if (! SIM->get_param_enum(BXPN_CPU_MODEL)->set_by_name(¶ms[i][6]))
+ PARSE_ERR(("%s: unsupported CPU model option.", context));
} else if (!strncmp(params[i], "ips=", 4)) {
SIM->get_param_num(BXPN_IPS)->set(atol(¶ms[i][4]));
#if BX_SUPPORT_SMP
@@ -2619,6 +2640,10 @@
#endif
} else if (!strncmp(params[i], "msrs=", 5)) {
SIM->get_param_string(BXPN_CONFIGURABLE_MSRS_PATH)->set(¶ms[i][5]);
+ } else if (!strncmp(params[i], "cpuid_limit_winnt=", 18)) {
+ if (parse_param_bool(params[i], 18, BXPN_CPUID_LIMIT_WINNT) < 0) {
+ PARSE_ERR(("%s: cpuid directive malformed.", context));
+ }
} else {
PARSE_ERR(("%s: cpu directive malformed.", context));
}
@@ -2645,10 +2670,6 @@
SIM->get_param_num(BXPN_CPUID_MODEL)->set(strtoul(¶ms[i][6], NULL, 0));
} else if (!strncmp(params[i], "family=", 7)) {
SIM->get_param_num(BXPN_CPUID_FAMILY)->set(strtoul(¶ms[i][7], NULL, 0));
- } else if (!strncmp(params[i], "cpuid_limit_winnt=", 18)) {
- if (parse_param_bool(params[i], 18, BXPN_CPUID_LIMIT_WINNT) < 0) {
- PARSE_ERR(("%s: cpuid directive malformed.", context));
- }
#if BX_CPU_LEVEL >= 5
} else if (!strncmp(params[i], "mmx=", 4)) {
if (parse_param_bool(params[i], 4, BXPN_CPUID_MMX) < 0) {
@@ -3958,8 +3979,9 @@
#else
fprintf(fp, "cpu: count=1, ips=%u, ", SIM->get_param_num(BXPN_IPS)->get());
#endif
- fprintf(fp, "reset_on_triple_fault=%d",
- SIM->get_param_bool(BXPN_RESET_ON_TRIPLE_FAULT)->get());
+ fprintf(fp, "reset_on_triple_fault=%d, cpuid_limit_winnt=%d",
+ SIM->get_param_bool(BXPN_RESET_ON_TRIPLE_FAULT)->get(),
+ SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get());
#if BX_CPU_LEVEL >= 5
fprintf(fp, ", ignore_bad_msrs=%d", \
SIM->get_param_bool(BXPN_IGNORE_BAD_MSRS)->get()); #endif
@@ -3971,7 +3993,10 @@
fprintf(fp, "\n");
#if BX_CPU_LEVEL >= 4
- fprintf(fp, "cpuid: cpuid_limit_winnt=%d", \
SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get()); + fprintf(fp, "cpuid: \
family=%d, model=0x%02x, stepping=%d", + \
SIM->get_param_num(BXPN_CPUID_FAMILY)->get(), + \
SIM->get_param_num(BXPN_CPUID_MODEL)->get(), + \
SIM->get_param_num(BXPN_CPUID_STEPPING)->get()); #if BX_CPU_LEVEL >= 5
fprintf(fp, ", mmx=%d, apic=%s", SIM->get_param_bool(BXPN_CPUID_MMX)->get(),
SIM->get_param_enum(BXPN_CPUID_APIC)->get_selected());
@@ -4004,16 +4029,12 @@
#endif
fprintf(fp, "\n");
- fprintf(fp, "cpuid: family=%d, model=0x%02x, stepping=%d",
- SIM->get_param_num(BXPN_CPUID_FAMILY)->get(),
- SIM->get_param_num(BXPN_CPUID_MODEL)->get(),
- SIM->get_param_num(BXPN_CPUID_STEPPING)->get());
const char *vendor_string = SIM->get_param_string(BXPN_VENDOR_STRING)->getptr();
if (vendor_string)
- fprintf(fp, ", vendor_string=\"%s\"", vendor_string);
+ fprintf(fp, "cpuid: vendor_string=\"%s\"\n", vendor_string);
const char *brand_string = SIM->get_param_string(BXPN_BRAND_STRING)->getptr();
if (brand_string)
- fprintf(fp, ", brand_string=\"%s\"", brand_string);
+ fprintf(fp, "cpuid: brand_string=\"%s\"\n", brand_string);
fprintf(fp, "\n");
#endif
Modified: trunk/bochs/cpu/Makefile.in
===================================================================
--- trunk/bochs/cpu/Makefile.in 2011-07-29 08:16:28 UTC (rev 10504)
+++ trunk/bochs/cpu/Makefile.in 2011-07-29 15:03:54 UTC (rev 10505)
@@ -35,8 +35,6 @@
X_PRE_LIBS = @X_PRE_LIBS@
RANLIB = @RANLIB@
-
-
BX_INCDIRS = -I.. -I$(srcdir)/.. -I../@INSTRUMENT_DIR@ \
-I$(srcdir)/../@INSTRUMENT_DIR@
# Objects which are synced between the cpu and cpu64 code and
@@ -128,6 +126,10 @@
bit64.o \
stack64.o
+CPUDB_OBJS = cpudb/corei7_sandy_bridge_2600K.o \
+ cpudb/core2_extreme_x9770.o \
+ cpudb/p4_prescott_celeron_336.o
+
BX_INCLUDES = ../bochs.h ../config.h
@@ -137,18 +139,22 @@
$(CXX) @DASH@c $(BX_INCDIRS) $(CXXFLAGS) @CXXFP@$< @OFP@$@
-libcpu.a: $(OBJS) @OBJS64@
+libcpu.a: $(OBJS) $(CPUDB_OBJS) @OBJS64@
@RMCOMMAND@ libcpu.a
- @MAKELIB@ $(OBJS) @OBJS64@
+ @MAKELIB@ $(OBJS) $(CPUDB_OBJS) @OBJS64@
$(RANLIB) libcpu.a
$(OBJS): $(BX_INCLUDES)
$(OBJS64): $(BX_INCLUDES)
+$(CPUDB_OBJS): $(BX_INCLUDES)
+
clean:
@RMCOMMAND@ *.o
@RMCOMMAND@ *.a
+ cd cpudb && @RMCOMMAND@ *.o *.a
+ @CD_UP_ONE@
dist-clean: clean
@RMCOMMAND@ Makefile
@@ -788,3 +794,24 @@
cpuid.h crregs.h descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h \
apic.h ../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h
+cpudb/corei7_sandy_bridge_2600K.o: cpudb/corei7_sandy_bridge_2600K.@CPP_SUFFIX@ \
../bochs.h ../config.h ../osdep.h \ + ../bx_debug/debug.h ../bxversion.h \
../gui/siminterface.h \ + ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
../plugin.h \ + ../extplugin.h ../gui/gui.h ../instrument/stubs/instrument.h cpu.h \
+ cpuid.h crregs.h descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h \
+ apic.h ../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
+ ../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h cpudb/corei7_sandy_bridge_2600K.h
+cpudb/core2_extreme_x9770.o: cpudb/core2_extreme_x9770.@CPP_SUFFIX@ ../bochs.h \
../config.h ../osdep.h \ + ../bx_debug/debug.h ../bxversion.h ../gui/siminterface.h \
+ ../gui/paramtree.h ../memory/memory.h ../pc_system.h ../plugin.h \
+ ../extplugin.h ../gui/gui.h ../instrument/stubs/instrument.h cpu.h \
+ cpuid.h crregs.h descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h \
+ apic.h ../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
+ ../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h cpudb/core2_extreme_x9770.h
+cpudb/p4_prescott_celeron_336.o: cpudb/p4_prescott_celeron_336.@CPP_SUFFIX@ \
../bochs.h ../config.h ../osdep.h \ + ../bx_debug/debug.h ../bxversion.h \
../gui/siminterface.h \ + ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
../plugin.h \ + ../extplugin.h ../gui/gui.h ../instrument/stubs/instrument.h cpu.h \
+ cpuid.h crregs.h descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h \
+ apic.h ../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
+ ../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h cpudb/p4_prescott_celeron_336.h
Added: trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc
===================================================================
--- trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc (rev 0)
+++ trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc 2011-07-29 15:03:54 UTC (rev 10505)
@@ -0,0 +1,601 @@
+/////////////////////////////////////////////////////////////////////////
+// $Id$
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2011 Stanislav Shwartsman
+// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+//
+/////////////////////////////////////////////////////////////////////////
+
+#include "bochs.h"
+#include "cpu/cpu.h"
+#include "param_names.h"
+#include "core2_extreme_x9770.h"
+
+#define LOG_THIS cpu->
+
+#if BX_SUPPORT_X86_64
+
+core2_extreme_x9770_t::core2_extreme_x9770_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
+{
+#if BX_SUPPORT_SMP
+ nthreads = SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
+ ncores = SIM->get_param_num(BXPN_CPU_NCORES)->get();
+ nprocessors = SIM->get_param_num(BXPN_CPU_NPROCESSORS)->get();
+#endif
+
+ if (! BX_SUPPORT_X86_64)
+ BX_PANIC(("You must enable x86-64 for Intel Core2 X9770 configuration"));
+}
+
+void core2_extreme_x9770_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, \
cpuid_function_t *leaf) +{
+ static bx_bool cpuid_limit_winnt = \
SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get(); + if (function > 3 && \
cpuid_limit_winnt) + function = 3;
+
+ switch(function) {
+ case 0x80000000:
+ get_ext_cpuid_leaf_0(leaf);
+ return;
+ case 0x80000001:
+ get_ext_cpuid_leaf_1(leaf);
+ return;
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
+ get_ext_cpuid_brand_string_leaf(function, leaf);
+ return;
+ case 0x80000005:
+ get_ext_cpuid_leaf_5(leaf);
+ return;
+ case 0x80000006:
+ get_ext_cpuid_leaf_6(leaf);
+ return;
+ case 0x80000007:
+ get_ext_cpuid_leaf_7(leaf);
+ return;
+ case 0x80000008:
+ get_ext_cpuid_leaf_8(leaf);
+ return;
+ case 0x00000000:
+ get_std_cpuid_leaf_0(leaf);
+ return;
+ case 0x00000001:
+ get_std_cpuid_leaf_1(leaf);
+ return;
+ case 0x00000002:
+ get_std_cpuid_leaf_2(leaf);
+ return;
+ case 0x00000003:
+ get_std_cpuid_leaf_3(leaf);
+ return;
+ case 0x00000004:
+ get_std_cpuid_leaf_4(subfunction, leaf);
+ return;
+ case 0x00000005:
+ get_std_cpuid_leaf_5(leaf);
+ return;
+ case 0x00000006:
+ get_std_cpuid_leaf_6(leaf);
+ return;
+ case 0x00000007:
+ get_std_cpuid_leaf_7(subfunction, leaf);
+ return;
+ case 0x00000008:
+ get_std_cpuid_leaf_8(leaf);
+ return;
+ case 0x00000009:
+ get_std_cpuid_leaf_9(leaf);
+ return;
+ case 0x0000000A:
+ default:
+ get_std_cpuid_leaf_A(leaf);
+ return;
+ }
+}
+
+Bit32u core2_extreme_x9770_t::get_isa_extensions_bitmask(void) const
+{
+ return BX_CPU_X87 |
+ BX_CPU_486 |
+ BX_CPU_PENTIUM |
+ BX_CPU_P6 |
+ BX_CPU_MMX |
+ BX_CPU_FXSAVE_FXRSTOR |
+ BX_CPU_SYSENTER_SYSEXIT |
+ BX_CPU_CLFLUSH |
+ BX_CPU_SSE |
+ BX_CPU_SSE2 |
+ BX_CPU_SSE3 |
+ BX_CPU_SSSE3 |
+ BX_CPU_SSE4_1 |
+#if BX_SUPPORT_MONITOR_MWAIT
+ BX_CPU_MONITOR_MWAIT |
+#endif
+#if BX_SUPPORT_VMX
+ BX_CPU_VMX |
+#endif
+ /* BX_CPU_SMX | */
+ BX_CPU_X86_64;
+}
+
+Bit32u core2_extreme_x9770_t::get_cpu_extensions_bitmask(void) const
+{
+ return BX_CPU_DEBUG_EXTENSIONS |
+ BX_CPU_VME |
+ BX_CPU_PSE |
+ BX_CPU_PAE |
+ BX_CPU_PGE |
+ BX_CPU_PSE36 |
+ BX_CPU_PAT_MTRR |
+ BX_CPU_XAPIC;
+}
+
+// leaf 0x00000000 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf)
+{
+ static const char* vendor_string = "GenuineIntel";
+
+ // EAX: highest std function understood by CPUID
+ // EBX: vendor ID string
+ // EDX: vendor ID string
+ // ECX: vendor ID string
+ leaf->eax = 0xa;
+
+ // CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
+ memcpy(&(leaf->ebx), vendor_string, 4);
+ memcpy(&(leaf->edx), vendor_string + 4, 4);
+ memcpy(&(leaf->ecx), vendor_string + 8, 4);
+#ifdef BX_BIG_ENDIAN
+ leaf->ebx = bx_bswap32(leaf->ebx);
+ leaf->ecx = bx_bswap32(leaf->ecx);
+ leaf->edx = bx_bswap32(leaf->edx);
+#endif
+}
+
+// leaf 0x00000001 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf)
+{
+ // EAX: CPU Version Information
+ // [3:0] Stepping ID
+ // [7:4] Model: starts at 1
+ // [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
+ // [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
+ // [19:16] Extended Model
+ // [27:20] Extended Family
+ leaf->eax = 0x00010676;
+
+ // EBX:
+ // [7:0] Brand ID
+ // [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
+ // [23:16] Number of logical processors in one physical processor
+ // [31:24] Local Apic ID
+
+ leaf->ebx = (CACHE_LINE_SIZE / 8) << 8;
+#if BX_SUPPORT_SMP
+ unsigned n_logical_processors = ncores*nthreads;
+ if (n_logical_processors > 1)
+ leaf->ebx |= (n_logical_processors << 16);
+#endif
+#if BX_SUPPORT_APIC
+ leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
+#endif
+
+ // ECX: Extended Feature Flags
+ // * [0:0] SSE3: SSE3 Instructions
+ // [1:1] PCLMULQDQ Instruction support
+ // * [2:2] DTES64: 64-bit DS area
+ // * [3:3] MONITOR/MWAIT support
+ // * [4:4] DS-CPL: CPL qualified debug store
+ // * [5:5] VMX: Virtual Machine Technology
+ // [6:6] SMX: Secure Virtual Machine Technology
+ // * [7:7] EST: Enhanced Intel SpeedStep Technology
+ // * [8:8] TM2: Thermal Monitor 2
+ // * [9:9] SSSE3: SSSE3 Instructions
+ // [10:10] CNXT-ID: L1 context ID
+ // [11:11] reserved
+ // [12:12] FMA Instructions support
+ // * [13:13] CMPXCHG16B: CMPXCHG16B instruction support
+ // * [14:14] xTPR update control
+ // * [15:15] PDCM - Perfon and Debug Capability MSR
+ // [16:16] reserved
+ // [17:17] PCID: Process Context Identifiers
+ // [18:18] DCA - Direct Cache Access
+ // * [19:19] SSE4.1 Instructions
+ // [20:20] SSE4.2 Instructions
+ // [21:21] X2APIC
+ // [22:22] MOVBE instruction
+ // [23:23] POPCNT instruction
+ // [24:24] TSC Deadline
+ // [25:25] AES Instructions
+ // [26:26] XSAVE extensions support
+ // [27:27] OSXSAVE support
+ // [28:28] AVX extensions support
+ // [29:29] AVX F16C - Float16 conversion support
+ // [30:30] RDRAND instruction
+ // [31:31] reserved
+ leaf->ecx = BX_CPUID_EXT_SSE3 |
+ BX_CPUID_EXT_DTES64 |
+#if BX_SUPPORT_MONITOR_MWAIT
+ BX_CPUID_EXT_MONITOR_MWAIT |
+#endif
+ BX_CPUID_EXT_DS_CPL |
+#if BX_SUPPORT_VMX
+ BX_CPUID_EXT_VMX |
+#endif
+ /* BX_CPUID_EXT_SMX | */
+ BX_CPUID_EXT_EST |
+ BX_CPUID_EXT_THERMAL_MONITOR2 |
+ BX_CPUID_EXT_SSSE3 |
+ BX_CPUID_EXT_CMPXCHG16B |
+ BX_CPUID_EXT_xTPR |
+ BX_CPUID_EXT_PDCM |
+ BX_CPUID_EXT_SSE4_1;
+
+ // EDX: Standard Feature Flags
+ // * [0:0] FPU on chip
+ // * [1:1] VME: Virtual-8086 Mode enhancements
+ // * [2:2] DE: Debug Extensions (I/O breakpoints)
+ // * [3:3] PSE: Page Size Extensions
+ // * [4:4] TSC: Time Stamp Counter
+ // * [5:5] MSR: RDMSR and WRMSR support
+ // * [6:6] PAE: Physical Address Extensions
+ // * [7:7] MCE: Machine Check Exception
+ // * [8:8] CXS: CMPXCHG8B instruction
+ // * [9:9] APIC: APIC on Chip
+ // [10:10] Reserved
+ // * [11:11] SYSENTER/SYSEXIT support
+ // * [12:12] MTRR: Memory Type Range Reg
+ // * [13:13] PGE/PTE Global Bit
+ // * [14:14] MCA: Machine Check Architecture
+ // * [15:15] CMOV: Cond Mov/Cmp Instructions
+ // * [16:16] PAT: Page Attribute Table
+ // * [17:17] PSE-36: Physical Address Extensions
+ // [18:18] PSN: Processor Serial Number
+ // * [19:19] CLFLUSH: CLFLUSH Instruction support
+ // [20:20] Reserved
+ // * [21:21] DS: Debug Store
+ // * [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
+ // * [23:23] MMX Technology
+ // * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
+ // * [25:25] SSE: SSE Extensions
+ // * [26:26] SSE2: SSE2 Extensions
+ // * [27:27] Self Snoop
+ // * [28:28] Hyper Threading Technology
+ // * [29:29] TM: Thermal Monitor
+ // [30:30] Reserved
+ // * [31:31] PBE: Pending Break Enable
+ leaf->edx = BX_CPUID_STD_X87 |
+ BX_CPUID_STD_VME |
+ BX_CPUID_STD_DEBUG_EXTENSIONS |
+ BX_CPUID_STD_PSE |
+ BX_CPUID_STD_TSC |
+ BX_CPUID_STD_MSR |
+ BX_CPUID_STD_PAE |
+ BX_CPUID_STD_MCE |
+ BX_CPUID_STD_CMPXCHG8B |
+ BX_CPUID_STD_SYSENTER_SYSEXIT |
+ BX_CPUID_STD_MTRR |
+ BX_CPUID_STD_GLOBAL_PAGES |
+ BX_CPUID_STD_MCA |
+ BX_CPUID_STD_CMOV |
+ BX_CPUID_STD_PAT |
+ BX_CPUID_STD_PSE36 |
+ BX_CPUID_STD_CLFLUSH |
+ BX_CPUID_STD_DEBUG_STORE |
+ BX_CPUID_STD_ACPI |
+ BX_CPUID_STD_MMX |
+ BX_CPUID_STD_FXSAVE_FXRSTOR |
+ BX_CPUID_STD_SSE |
+ BX_CPUID_STD_SSE2 |
+ BX_CPUID_STD_SELF_SNOOP |
+ BX_CPUID_STD_HT |
+ BX_CPUID_STD_THERMAL_MONITOR |
+ BX_CPUID_STD_PBE;
+#if BX_SUPPORT_APIC
+ // if MSR_APICBASE APIC Global Enable bit has been cleared,
+ // the CPUID feature flag for the APIC is set to 0.
+ if (cpu->msr.apicbase & 0x800)
+ leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
+#endif
+}
+
+// leaf 0x00000002 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_2(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000002 - Cache and TLB Descriptors
+ leaf->eax = 0x05B0B101;
+ leaf->ebx = 0x005657F0;
+ leaf->ecx = 0x00000000;
+ leaf->edx = 0x2CB4304E;
+}
+
+// leaf 0x00000003 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_3(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000003 - Processor Serial Number
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x00000004 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_4(Bit32u subfunction, \
cpuid_function_t *leaf) +{
+ // CPUID function 0x00000004 - Deterministic Cache Parameters
+ switch(subfunction) {
+ case 0:
+ leaf->eax = 0x0C000121;
+ leaf->ebx = 0x01C0003F;
+ leaf->ecx = 0x0000003F;
+ leaf->edx = 0x00000001;
+ return;
+ case 1:
+ leaf->eax = 0x0C000122;
+ leaf->ebx = 0x01C0003F;
+ leaf->ecx = 0x0000003F;
+ leaf->edx = 0x00000001;
+ return;
+ case 2:
+ leaf->eax = 0x0C004143;
+ leaf->ebx = 0x05C0003F;
+ leaf->ecx = 0x00000FFF;
+ leaf->edx = 0x00000001;
+ return;
+ default:
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+ }
+}
+
+// leaf 0x00000005 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_5(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000005 - MONITOR/MWAIT Leaf
+
+#if BX_SUPPORT_MONITOR_MWAIT
+ // EAX - Smallest monitor-line size in bytes
+ // EBX - Largest monitor-line size in bytes
+ // ECX -
+ // [31:2] - reserved
+ // [1:1] - exit MWAIT even with EFLAGS.IF = 0
+ // [0:0] - MONITOR/MWAIT extensions are supported
+ // EDX - Reserved
+ leaf->eax = CACHE_LINE_SIZE;
+ leaf->ebx = CACHE_LINE_SIZE;
+ leaf->ecx = 3;
+ leaf->edx = 0;
+#else
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+#endif
+}
+
+// leaf 0x00000006 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_6(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000006 - Thermal and Power Management Leaf
+ leaf->eax = 0x00000001;
+ leaf->ebx = 0x00000002;
+ leaf->ecx = 0x00000001;
+ leaf->edx = 0x00000000;
+}
+
+// leaf 0x00000007 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_7(Bit32u subfunction, \
cpuid_function_t *leaf) +{
+ leaf->eax = 0; /* leaf 7 not supported */
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x00000008 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_8(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000008 - reserved
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x00000009 //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_9(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000009 - Direct Cache Access Information
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x0000000A //
+void core2_extreme_x9770_t::get_std_cpuid_leaf_A(cpuid_function_t *leaf)
+{
+ // CPUID function 0x0000000A - Architectural Performance Monitoring Leaf
+ leaf->eax = 0x07280202;
+ leaf->ebx = 0x00000000;
+ leaf->ecx = 0x00000000;
+ leaf->edx = 0x00000503;
+
+ BX_INFO(("WARNING: Architectural Performance Monitoring is not implemented"));
+}
+
+// leaf 0x80000000 //
+void core2_extreme_x9770_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf)
+{
+ // EAX: highest extended function understood by CPUID
+ // EBX: reserved
+ // EDX: reserved
+ // ECX: reserved
+ leaf->eax = 0x80000008;
+ leaf->ebx = 0;
+ leaf->edx = 0; // Reserved for Intel
+ leaf->ecx = 0;
+}
+
+// leaf 0x80000001 //
+void core2_extreme_x9770_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf)
+{
+ // EAX: CPU Version Information (reserved for Intel)
+ leaf->eax = 0;
+
+ // EBX: Brand ID (reserved for Intel)
+ leaf->ebx = 0;
+
+ // ECX:
+ // * [0:0] LAHF/SAHF instructions support in 64-bit mode
+ // [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
+ // [2:2] SVM: Secure Virtual Machine (AMD)
+ // [3:3] Extended APIC Space
+ // [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
+ // [5:5] LZCNT: LZCNT instruction support
+ // [6:6] SSE4A: SSE4A Instructions support (deprecated?)
+ // [7:7] Misaligned SSE support
+ // [8:8] PREFETCHW: PREFETCHW instruction support
+ // [9:9] OSVW: OS visible workarounds (AMD)
+ // [11:10] reserved
+ // [12:12] SKINIT support
+ // [13:13] WDT: Watchdog timer support
+ // [31:14] reserved
+
+ leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF;
+
+ // EDX:
+ // Many of the bits in EDX are the same as EAX [*] for AMD
+ // [10:0] Reserved for Intel
+ // * [11:11] SYSCALL/SYSRET support
+ // [19:12] Reserved for Intel
+ // * [20:20] No-Execute page protection
+ // [25:21] Reserved
+ // [26:26] 1G paging support
+ // [27:27] Support RDTSCP Instruction
+ // [28:28] Reserved
+ // * [29:29] Long Mode
+ // [30:30] AMD 3DNow! Extensions
+ // [31:31] AMD 3DNow! Instructions
+
+ leaf->edx = BX_CPUID_STD2_SYSCALL_SYSRET |
+ BX_CPUID_STD2_NX |
+ BX_CPUID_STD2_LONG_MODE;
+}
+
+// leaf 0x80000002 //
+// leaf 0x80000003 //
+// leaf 0x80000004 //
+void core2_extreme_x9770_t::get_ext_cpuid_brand_string_leaf(Bit32u function, \
cpuid_function_t *leaf) +{
+ // CPUID function 0x800000002-0x800000004 - Processor Name String Identifier
+ static const char* brand_string = "Intel(R) Core(TM)2 Extreme CPU X9770 @ \
3.20GHz"; +
+ switch(function) {
+ case 0x80000002:
+ memcpy(&(leaf->eax), brand_string , 4);
+ memcpy(&(leaf->ebx), brand_string + 4, 4);
+ memcpy(&(leaf->ecx), brand_string + 8, 4);
+ memcpy(&(leaf->edx), brand_string + 12, 4);
+ break;
+ case 0x80000003:
+ memcpy(&(leaf->eax), brand_string + 16, 4);
+ memcpy(&(leaf->ebx), brand_string + 20, 4);
+ memcpy(&(leaf->ecx), brand_string + 24, 4);
+ memcpy(&(leaf->edx), brand_string + 28, 4);
+ break;
+ case 0x80000004:
+ memcpy(&(leaf->eax), brand_string + 32, 4);
+ memcpy(&(leaf->ebx), brand_string + 36, 4);
+ memcpy(&(leaf->ecx), brand_string + 40, 4);
+ memcpy(&(leaf->edx), brand_string + 44, 4);
+ break;
+ default:
+ break;
+ }
+
+#ifdef BX_BIG_ENDIAN
+ leaf->eax = bx_bswap32(leaf->eax);
+ leaf->ebx = bx_bswap32(leaf->ebx);
+ leaf->ecx = bx_bswap32(leaf->ecx);
+ leaf->edx = bx_bswap32(leaf->edx);
+#endif
+}
+
+// leaf 0x80000005 //
+void core2_extreme_x9770_t::get_ext_cpuid_leaf_5(cpuid_function_t *leaf)
+{
+ // CPUID function 0x800000005 - L1 Cache and TLB Identifiers
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0; // reserved for Intel
+ leaf->edx = 0;
+}
+
+// leaf 0x80000006 //
+void core2_extreme_x9770_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf)
+{
+ // CPUID function 0x800000006 - L2 Cache and TLB Identifiers
+ leaf->eax = 0x00000000;
+ leaf->ebx = 0x00000000;
+ leaf->ecx = 0x18008040;
+ leaf->edx = 0x00000000;
+}
+
+// leaf 0x80000007 //
+void core2_extreme_x9770_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf)
+{
+ // CPUID function 0x800000007 - Advanced Power Management
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x80000008 //
+void core2_extreme_x9770_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf)
+{
+ // virtual & phys address size in low 2 bytes.
+ leaf->eax = BX_PHY_ADDRESS_WIDTH | (BX_LIN_ADDRESS_WIDTH << 8);
+ leaf->ebx = 0;
+ leaf->ecx = 0; // Reserved, undefined
+ leaf->edx = 0;
+}
+
+void core2_extreme_x9770_t::dump_cpuid(void)
+{
+ struct cpuid_function_t leaf;
+ unsigned n;
+
+ for (n=0; n<=0xa; n++) {
+ BX_CPU_THIS_PTR cpuid->get_cpuid_leaf(n, 0x00000000, &leaf);
+ BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, \
leaf.edx)); + }
+
+ for (n=0x80000000; n<=0x80000008; n++) {
+ BX_CPU_THIS_PTR cpuid->get_cpuid_leaf(n, 0x00000000, &leaf);
+ BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, \
leaf.edx)); + }
+}
+
+bx_cpuid_t *create_core2_extreme_x9770_cpuid(BX_CPU_C *cpu) { return new \
core2_extreme_x9770_t(cpu); } +
+#endif
Property changes on: trunk/bochs/cpu/cpudb/core2_extreme_x9770.cc
___________________________________________________________________
Added: svn:executable
+ *
Added: svn:keywords
+ Author Date Id Rev
Added: trunk/bochs/cpu/cpudb/core2_extreme_x9770.h
===================================================================
--- trunk/bochs/cpu/cpudb/core2_extreme_x9770.h (rev 0)
+++ trunk/bochs/cpu/cpudb/core2_extreme_x9770.h 2011-07-29 15:03:54 UTC (rev 10505)
@@ -0,0 +1,74 @@
+/////////////////////////////////////////////////////////////////////////
+// $Id$
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2011 Stanislav Shwartsman
+// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+//
+/////////////////////////////////////////////////////////////////////////
+
+#ifndef BX_GENERIC_CPUID_DEFINITIONS_H
+#define BX_GENERIC_CPUID_DEFINITIONS_H
+
+#include "cpu/cpuid.h"
+
+class core2_extreme_x9770_t : public bx_cpuid_t {
+public:
+ core2_extreme_x9770_t(BX_CPU_C *cpu);
+ virtual ~core2_extreme_x9770_t() {}
+
+ // return CPU name
+ virtual const char *get_name(void) const { return "core2_extreme_x9770"; }
+
+ virtual Bit32u get_isa_extensions_bitmask(void) const;
+ virtual Bit32u get_cpu_extensions_bitmask(void) const;
+
+ virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t \
*leaf); +
+ virtual void dump_cpuid(void);
+
+private:
+#if BX_SUPPORT_SMP
+ unsigned nprocessors;
+ unsigned ncores;
+ unsigned nthreads;
+#endif
+
+ void get_std_cpuid_leaf_0(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_1(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_2(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_3(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_5(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_6(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_7(Bit32u subfunction, cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_8(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_9(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_A(cpuid_function_t *leaf);
+
+ void get_ext_cpuid_leaf_0(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_1(cpuid_function_t *leaf);
+ void get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_5(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_6(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_7(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_8(cpuid_function_t *leaf);
+};
+
+extern bx_cpuid_t *create_core2_extreme_x9770_cpuid(BX_CPU_C *cpu);
+
+#endif
Property changes on: trunk/bochs/cpu/cpudb/core2_extreme_x9770.h
___________________________________________________________________
Added: svn:executable
+ *
Added: svn:keywords
+ Author Date Id Rev
Added: trunk/bochs/cpu/cpudb/core2_extreme_x9770.txt
===================================================================
--- trunk/bochs/cpu/cpudb/core2_extreme_x9770.txt (rev 0)
+++ trunk/bochs/cpu/cpudb/core2_extreme_x9770.txt 2011-07-29 15:03:54 UTC (rev 10505)
@@ -0,0 +1,245 @@
+CPU-Z TXT Report
+-------------------------------------------------------------------------
+
+Binaries
+-------------------------------------------------------------------------
+
+CPU-Z version 1.53
+
+Processors
+-------------------------------------------------------------------------
+
+Number of processors 1
+Number of threads 4
+
+APICs
+-------------------------------------------------------------------------
+
+Processor 0
+ -- Core 0
+ -- Thread 0 0
+ -- Core 1
+ -- Thread 0 1
+ -- Core 3
+ -- Thread 0 3
+ -- Core 2
+ -- Thread 0 2
+
+Processors Information
+-------------------------------------------------------------------------
+
+Processor 1 ID = 0
+ Number of cores 4 (max 4)
+ Number of threads 4 (max 4)
+ Name Intel Core 2 Extreme QX9770
+ Codename Yorkfield
+ Specification Intel(R) Core(TM)2 Extreme CPU X9770 @ 3.20GHz
+ Package (platform ID) Socket 775 LGA (0x4)
+ CPUID 6.7.6
+ Extended CPUID 6.17
+ Core Stepping C0
+ Technology 45 nm
+ Core Speed 2397.7 MHz
+ Multiplier x FSB 6.0 x 399.6 MHz
+ Rated Bus speed 1598.5 MHz
+ Stock frequency 3200 MHz
+ Instructions sets MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, EM64T, VT-x
+ L1 Data cache 4 x 32 KBytes, 8-way set associative, 64-byte line size
+ L1 Instruction cache 4 x 32 KBytes, 8-way set associative, 64-byte line size
+ L2 cache 2 x 6144 KBytes, 24-way set associative, 64-byte line size
+ FID/VID Control yes
+ FID range 6.0x - 8.0x
+ Max VID 1.288 V
+
+
+
+Thread dumps
+-------------------------------------------------------------------------
+
+CPU Thread 0
+ APIC ID 0
+ Topology Processor ID 0, Core ID 0, Thread ID 0
+ Type 01008002h
+ Max CPUID level 0000000Ah
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 1 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 1 thread(s)
+ Cache descriptor Level 2, U, 6 MB, 2 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000A 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x00010676 0x00040800 0x0008E3BD 0xBFEBFBFF
+ 0x00000002 0x05B0B101 0x005657F0 0x00000000 0x2CB4304E
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x0C000121 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C000122 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C004143 0x05C0003F 0x00000FFF 0x00000001
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00000020
+ 0x00000006 0x00000001 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000400 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07280202 0x00000000 0x00000000 0x00000503
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x20100000
+ 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865
+ 0x80000003 0x45203229 0x65727478 0x4320656D 0x58205550
+ 0x80000004 0x30373739 0x20402020 0x30322E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x18008040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00900
+ MSR 0x00000017 0x0C100000 0x88C40825
+ MSR 0x000000CD 0x00000000 0x00000806
+ MSR 0x0000003F 0x00000000 0x00000000
+ MSR 0x000000CE 0x001A0825 0x7F7F0716
+ MSR 0x000001A0 0x00000040 0x62872489
+ MSR 0x000000EE 0x00000000 0x877D4B00
+ MSR 0x0000011E 0x00000000 0xBE702111
+ MSR 0x00000194 0x00000000 0x00010825
+ MSR 0x0000019C 0x00000000 0x882E0000
+ MSR 0x00000198 0x061A0825 0x86000825
+ MSR 0x00000199 0x00000000 0x00000825
+
+CPU Thread 1
+ APIC ID 1
+ Topology Processor ID 0, Core ID 1, Thread ID 0
+ Type 01008002h
+ Max CPUID level 0000000Ah
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 1 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 1 thread(s)
+ Cache descriptor Level 2, U, 6 MB, 2 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000A 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x00010676 0x01040800 0x0008E3BD 0xBFEBFBFF
+ 0x00000002 0x05B0B101 0x005657F0 0x00000000 0x2CB4304E
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x0C000121 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C000122 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C004143 0x05C0003F 0x00000FFF 0x00000001
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00000020
+ 0x00000006 0x00000001 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000400 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07280202 0x00000000 0x00000000 0x00000503
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x20100000
+ 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865
+ 0x80000003 0x45203229 0x65727478 0x4320656D 0x58205550
+ 0x80000004 0x30373739 0x20402020 0x30322E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x18008040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00800
+ MSR 0x00000017 0x0C100000 0x88C40825
+ MSR 0x000000CD 0x00000000 0x00000806
+ MSR 0x0000003F 0x00000000 0x00000000
+ MSR 0x000000CE 0x001A0825 0x7F7F0716
+ MSR 0x000001A0 0x00000040 0x62872489
+ MSR 0x000000EE 0x00000000 0x877D4B00
+ MSR 0x0000011E 0x00000000 0xBE702111
+ MSR 0x00000194 0x00000000 0x00010825
+ MSR 0x0000019C 0x00000000 0x882E0000
+ MSR 0x00000198 0x061A0825 0x8600061A
+ MSR 0x00000199 0x00000000 0x0000061A
+
+CPU Thread 2
+ APIC ID 3
+ Topology Processor ID 0, Core ID 3, Thread ID 0
+ Type 01008002h
+ Max CPUID level 0000000Ah
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 1 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 1 thread(s)
+ Cache descriptor Level 2, U, 6 MB, 2 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000A 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x00010676 0x03040800 0x0008E3BD 0xBFEBFBFF
+ 0x00000002 0x05B0B101 0x005657F0 0x00000000 0x2CB4304E
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x0C000121 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C000122 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C004143 0x05C0003F 0x00000FFF 0x00000001
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00000020
+ 0x00000006 0x00000001 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000400 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07280202 0x00000000 0x00000000 0x00000503
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x20100000
+ 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865
+ 0x80000003 0x45203229 0x65727478 0x4320656D 0x58205550
+ 0x80000004 0x30373739 0x20402020 0x30322E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x18008040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00800
+ MSR 0x00000017 0x0C100000 0x88C40825
+ MSR 0x000000CD 0x00000000 0x00000806
+ MSR 0x0000003F 0x00000000 0x00000000
+ MSR 0x000000CE 0x001A0825 0x7F7F0716
+ MSR 0x000001A0 0x00000040 0x62852489
+ MSR 0x000000EE 0x00000000 0x877D4B00
+ MSR 0x0000011E 0x00000000 0xBE702111
+ MSR 0x00000194 0x00000000 0x00010825
+ MSR 0x0000019C 0x00000000 0x88500000
+ MSR 0x00000198 0x061A0825 0x86000825
+ MSR 0x00000199 0x00000000 0x00000825
+
+CPU Thread 3
+ APIC ID 2
+ Topology Processor ID 0, Core ID 2, Thread ID 0
+ Type 01008002h
+ Max CPUID level 0000000Ah
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 1 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 1 thread(s)
+ Cache descriptor Level 2, U, 6 MB, 2 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000A 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x00010676 0x02040800 0x0008E3BD 0xBFEBFBFF
+ 0x00000002 0x05B0B101 0x005657F0 0x00000000 0x2CB4304E
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x0C000121 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C000122 0x01C0003F 0x0000003F 0x00000001
+ 0x00000004 0x0C004143 0x05C0003F 0x00000FFF 0x00000001
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00000020
+ 0x00000006 0x00000001 0x00000002 0x00000001 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000400 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07280202 0x00000000 0x00000000 0x00000503
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x20100000
+ 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865
+ 0x80000003 0x45203229 0x65727478 0x4320656D 0x58205550
+ 0x80000004 0x30373739 0x20402020 0x30322E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x18008040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00800
+ MSR 0x00000017 0x0C100000 0x88C40825
+ MSR 0x000000CD 0x00000000 0x00000806
+ MSR 0x0000003F 0x00000000 0x00000000
+ MSR 0x000000CE 0x001A0825 0x7F7F0716
+ MSR 0x000001A0 0x00000040 0x62852489
+ MSR 0x000000EE 0x00000000 0x877D4B00
+ MSR 0x0000011E 0x00000000 0xBE702111
+ MSR 0x00000194 0x00000000 0x00010825
+ MSR 0x0000019C 0x00000000 0x88500000
+ MSR 0x00000198 0x061A0825 0x86000825
+ MSR 0x00000199 0x00000000 0x00000825
Property changes on: trunk/bochs/cpu/cpudb/core2_extreme_x9770.txt
___________________________________________________________________
Added: svn:executable
+ *
Added: trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc
===================================================================
--- trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc (rev \
0)
+++ trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc 2011-07-29 15:03:54 UTC (rev \
10505) @@ -0,0 +1,772 @@
+/////////////////////////////////////////////////////////////////////////
+// $Id$
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2011 Stanislav Shwartsman
+// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+//
+/////////////////////////////////////////////////////////////////////////
+
+#include "bochs.h"
+#include "cpu/cpu.h"
+#include "param_names.h"
+#include "corei7_sandy_bridge_2600K.h"
+
+#define LOG_THIS cpu->
+
+#if BX_SUPPORT_X86_64 && BX_SUPPORT_AVX
+
+corei7_sandy_bridge_2600k_t::corei7_sandy_bridge_2600k_t(BX_CPU_C *cpu): \
bx_cpuid_t(cpu) +{
+#if BX_SUPPORT_SMP
+ nthreads = SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
+ ncores = SIM->get_param_num(BXPN_CPU_NCORES)->get();
+ nprocessors = SIM->get_param_num(BXPN_CPU_NPROCESSORS)->get();
+#endif
+
+ if (! BX_SUPPORT_X86_64)
+ BX_PANIC(("You must enable x86-64 for Intel Core2 Sandy Bridge configuration"));
+
+ if (! BX_SUPPORT_AVX)
+ BX_PANIC(("You must enable AVX for Intel Core2 Sandy Bridge configuration"));
+
+ BX_INFO(("WARNING: TSC deadline is not implemented yet"));
+}
+
+void corei7_sandy_bridge_2600k_t::get_cpuid_leaf(Bit32u function, Bit32u \
subfunction, cpuid_function_t *leaf) +{
+ static bx_bool cpuid_limit_winnt = \
SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get(); + if (function > 3 && \
cpuid_limit_winnt) + function = 3;
+
+ switch(function) {
+ case 0x80000000:
+ get_ext_cpuid_leaf_0(leaf);
+ return;
+ case 0x80000001:
+ get_ext_cpuid_leaf_1(leaf);
+ return;
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
+ get_ext_cpuid_brand_string_leaf(function, leaf);
+ return;
+ case 0x80000005:
+ get_ext_cpuid_leaf_5(leaf);
+ return;
+ case 0x80000006:
+ get_ext_cpuid_leaf_6(leaf);
+ return;
+ case 0x80000007:
+ get_ext_cpuid_leaf_7(leaf);
+ return;
+ case 0x80000008:
+ get_ext_cpuid_leaf_8(leaf);
+ return;
+ case 0x00000000:
+ get_std_cpuid_leaf_0(leaf);
+ return;
+ case 0x00000001:
+ get_std_cpuid_leaf_1(leaf);
+ return;
+ case 0x00000002:
+ get_std_cpuid_leaf_2(leaf);
+ return;
+ case 0x00000003:
+ get_std_cpuid_leaf_3(leaf);
+ return;
+ case 0x00000004:
+ get_std_cpuid_leaf_4(subfunction, leaf);
+ return;
+ case 0x00000005:
+ get_std_cpuid_leaf_5(leaf);
+ return;
+ case 0x00000006:
+ get_std_cpuid_leaf_6(leaf);
+ return;
+ case 0x00000007:
+ get_std_cpuid_leaf_7(subfunction, leaf);
+ return;
+ case 0x00000008:
+ get_std_cpuid_leaf_8(leaf);
+ return;
+ case 0x00000009:
+ get_std_cpuid_leaf_9(leaf);
+ return;
+ case 0x0000000A:
+ get_std_cpuid_leaf_A(leaf);
+ return;
+ case 0x0000000B:
+ get_std_cpuid_extended_topology_leaf(subfunction, leaf);
+ return;
+ case 0x0000000C:
+ get_std_cpuid_leaf_C(leaf);
+ return;
+ case 0x0000000D:
+ default:
+ get_std_cpuid_xsave_leaf(subfunction, leaf);
+ return;
+ }
+}
+
+Bit32u corei7_sandy_bridge_2600k_t::get_isa_extensions_bitmask(void) const
+{
+ return BX_CPU_X87 |
+ BX_CPU_486 |
+ BX_CPU_PENTIUM |
+ BX_CPU_P6 |
+ BX_CPU_MMX |
+ BX_CPU_FXSAVE_FXRSTOR |
+ BX_CPU_SYSENTER_SYSEXIT |
+ BX_CPU_CLFLUSH |
+ BX_CPU_SSE |
+ BX_CPU_SSE2 |
+ BX_CPU_SSE3 |
+ BX_CPU_SSSE3 |
+ BX_CPU_SSE4_1 |
+ BX_CPU_SSE4_2 |
+#if BX_SUPPORT_MONITOR_MWAIT
+ BX_CPU_MONITOR_MWAIT |
+#endif
+#if BX_SUPPORT_VMX
+ BX_CPU_VMX |
+#endif
+ /* BX_CPU_SMX | */
+ BX_CPU_XSAVE |
+ BX_CPU_XSAVEOPT |
+ BX_CPU_AES_PCLMULQDQ |
+ BX_CPU_AVX |
+ BX_CPU_X86_64;
+}
+
+Bit32u corei7_sandy_bridge_2600k_t::get_cpu_extensions_bitmask(void) const
+{
+ return BX_CPU_DEBUG_EXTENSIONS |
+ BX_CPU_VME |
+ BX_CPU_PSE |
+ BX_CPU_PAE |
+ BX_CPU_PGE |
+ BX_CPU_PSE36 |
+ BX_CPU_PAT_MTRR |
+ BX_CPU_XAPIC |
+ BX_CPU_X2APIC |
+ BX_CPU_PCID;
+}
+
+// leaf 0x00000000 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf)
+{
+ static const char* vendor_string = "GenuineIntel";
+
+ // EAX: highest std function understood by CPUID
+ // EBX: vendor ID string
+ // EDX: vendor ID string
+ // ECX: vendor ID string
+ leaf->eax = 0xd;
+
+ // CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
+ memcpy(&(leaf->ebx), vendor_string, 4);
+ memcpy(&(leaf->edx), vendor_string + 4, 4);
+ memcpy(&(leaf->ecx), vendor_string + 8, 4);
+#ifdef BX_BIG_ENDIAN
+ leaf->ebx = bx_bswap32(leaf->ebx);
+ leaf->ecx = bx_bswap32(leaf->ecx);
+ leaf->edx = bx_bswap32(leaf->edx);
+#endif
+}
+
+// leaf 0x00000001 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf)
+{
+ // EAX: CPU Version Information
+ // [3:0] Stepping ID
+ // [7:4] Model: starts at 1
+ // [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
+ // [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
+ // [19:16] Extended Model
+ // [27:20] Extended Family
+ leaf->eax = 0x000206a7;
+
+ // EBX:
+ // [7:0] Brand ID
+ // [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
+ // [23:16] Number of logical processors in one physical processor
+ // [31:24] Local Apic ID
+
+ leaf->ebx = (CACHE_LINE_SIZE / 8) << 8;
+#if BX_SUPPORT_SMP
+ unsigned n_logical_processors = ncores*nthreads;
+ if (n_logical_processors > 1)
+ leaf->ebx |= (n_logical_processors << 16);
+#endif
+#if BX_SUPPORT_APIC
+ leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
+#endif
+
+ // ECX: Extended Feature Flags
+ // * [0:0] SSE3: SSE3 Instructions
+ // * [1:1] PCLMULQDQ Instruction support
+ // * [2:2] DTES64: 64-bit DS area
+ // * [3:3] MONITOR/MWAIT support
+ // * [4:4] DS-CPL: CPL qualified debug store
+ // * [5:5] VMX: Virtual Machine Technology
+ // [6:6] SMX: Secure Virtual Machine Technology
+ // * [7:7] EST: Enhanced Intel SpeedStep Technology
+ // * [8:8] TM2: Thermal Monitor 2
+ // * [9:9] SSSE3: SSSE3 Instructions
+ // [10:10] CNXT-ID: L1 context ID
+ // [11:11] reserved
+ // [12:12] FMA Instructions support
+ // * [13:13] CMPXCHG16B: CMPXCHG16B instruction support
+ // * [14:14] xTPR update control
+ // * [15:15] PDCM - Perfon and Debug Capability MSR
+ // [16:16] reserved
+ // * [17:17] PCID: Process Context Identifiers
+ // [18:18] DCA - Direct Cache Access
+ // * [19:19] SSE4.1 Instructions
+ // * [20:20] SSE4.2 Instructions
+ // [21:21] X2APIC
+ // [22:22] MOVBE instruction
+ // * [23:23] POPCNT instruction
+ // * [24:24] TSC Deadline
+ // * [25:25] AES Instructions
+ // * [26:26] XSAVE extensions support
+ // * [27:27] OSXSAVE support
+ // * [28:28] AVX extensions support
+ // [29:29] AVX F16C - Float16 conversion support
+ // [30:30] RDRAND instruction
+ // [31:31] reserved
+ leaf->ecx = BX_CPUID_EXT_SSE3 |
+ BX_CPUID_EXT_PCLMULQDQ |
+ BX_CPUID_EXT_DTES64 |
+#if BX_SUPPORT_MONITOR_MWAIT
+ BX_CPUID_EXT_MONITOR_MWAIT |
+#endif
+ BX_CPUID_EXT_DS_CPL |
+#if BX_SUPPORT_VMX
+ BX_CPUID_EXT_VMX |
+#endif
+ /* BX_CPUID_EXT_SMX | */
+ BX_CPUID_EXT_EST |
+ BX_CPUID_EXT_THERMAL_MONITOR2 |
+ BX_CPUID_EXT_SSSE3 |
+ BX_CPUID_EXT_CMPXCHG16B |
+ BX_CPUID_EXT_xTPR |
+ BX_CPUID_EXT_PDCM |
+ BX_CPUID_EXT_PCID |
+ BX_CPUID_EXT_SSE4_1 |
+ BX_CPUID_EXT_SSE4_2 |
+ /* BX_CPUID_EXT_X2APIC | */
+ BX_CPUID_EXT_POPCNT |
+ BX_CPUID_EXT_TSC_DEADLINE |
+ BX_CPUID_EXT_AES |
+ BX_CPUID_EXT_XSAVE |
+ BX_CPUID_EXT_AVX;
+ if (cpu->cr4.get_OSXSAVE())
+ leaf->ecx |= BX_CPUID_EXT_OSXSAVE;
+
+ // EDX: Standard Feature Flags
+ // * [0:0] FPU on chip
+ // * [1:1] VME: Virtual-8086 Mode enhancements
+ // * [2:2] DE: Debug Extensions (I/O breakpoints)
+ // * [3:3] PSE: Page Size Extensions
+ // * [4:4] TSC: Time Stamp Counter
+ // * [5:5] MSR: RDMSR and WRMSR support
+ // * [6:6] PAE: Physical Address Extensions
+ // * [7:7] MCE: Machine Check Exception
+ // * [8:8] CXS: CMPXCHG8B instruction
+ // * [9:9] APIC: APIC on Chip
+ // [10:10] Reserved
+ // * [11:11] SYSENTER/SYSEXIT support
+ // * [12:12] MTRR: Memory Type Range Reg
+ // * [13:13] PGE/PTE Global Bit
+ // * [14:14] MCA: Machine Check Architecture
+ // * [15:15] CMOV: Cond Mov/Cmp Instructions
+ // * [16:16] PAT: Page Attribute Table
+ // * [17:17] PSE-36: Physical Address Extensions
+ // [18:18] PSN: Processor Serial Number
+ // * [19:19] CLFLUSH: CLFLUSH Instruction support
+ // [20:20] Reserved
+ // * [21:21] DS: Debug Store
+ // * [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
+ // * [23:23] MMX Technology
+ // * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
+ // * [25:25] SSE: SSE Extensions
+ // * [26:26] SSE2: SSE2 Extensions
+ // * [27:27] Self Snoop
+ // * [28:28] Hyper Threading Technology
+ // * [29:29] TM: Thermal Monitor
+ // [30:30] Reserved
+ // * [31:31] PBE: Pending Break Enable
+ leaf->edx = BX_CPUID_STD_X87 |
+ BX_CPUID_STD_VME |
+ BX_CPUID_STD_DEBUG_EXTENSIONS |
+ BX_CPUID_STD_PSE |
+ BX_CPUID_STD_TSC |
+ BX_CPUID_STD_MSR |
+ BX_CPUID_STD_PAE |
+ BX_CPUID_STD_MCE |
+ BX_CPUID_STD_CMPXCHG8B |
+ BX_CPUID_STD_SYSENTER_SYSEXIT |
+ BX_CPUID_STD_MTRR |
+ BX_CPUID_STD_GLOBAL_PAGES |
+ BX_CPUID_STD_MCA |
+ BX_CPUID_STD_CMOV |
+ BX_CPUID_STD_PAT |
+ BX_CPUID_STD_PSE36 |
+ BX_CPUID_STD_CLFLUSH |
+ BX_CPUID_STD_DEBUG_STORE |
+ BX_CPUID_STD_ACPI |
+ BX_CPUID_STD_MMX |
+ BX_CPUID_STD_FXSAVE_FXRSTOR |
+ BX_CPUID_STD_SSE |
+ BX_CPUID_STD_SSE2 |
+ BX_CPUID_STD_SELF_SNOOP |
+ BX_CPUID_STD_HT |
+ BX_CPUID_STD_THERMAL_MONITOR |
+ BX_CPUID_STD_PBE;
+#if BX_SUPPORT_APIC
+ // if MSR_APICBASE APIC Global Enable bit has been cleared,
+ // the CPUID feature flag for the APIC is set to 0.
+ if (cpu->msr.apicbase & 0x800)
+ leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
+#endif
+}
+
+// leaf 0x00000002 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_2(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000002 - Cache and TLB Descriptors
+ leaf->eax = 0x76035A01;
+ leaf->ebx = 0x00F0B0FF;
+ leaf->ecx = 0x00000000;
+ leaf->edx = 0x00CA0000;
+}
+
+// leaf 0x00000003 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_3(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000003 - Processor Serial Number
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x00000004 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_4(Bit32u subfunction, \
cpuid_function_t *leaf) +{
+ // CPUID function 0x00000004 - Deterministic Cache Parameters
+ switch(subfunction) {
+ case 0:
+ leaf->eax = 0x1C004121;
+ leaf->ebx = 0x01C0003F;
+ leaf->ecx = 0x0000003F;
+ leaf->edx = 0x00000000;
+ return;
+ case 1:
+ leaf->eax = 0x1C004122;
+ leaf->ebx = 0x01C0003F;
+ leaf->ecx = 0x0000003F;
+ leaf->edx = 0x00000000;
+ return;
+ case 2:
+ leaf->eax = 0x1C004143;
+ leaf->ebx = 0x01C0003F;
+ leaf->ecx = 0x000001FF;
+ leaf->edx = 0x00000000;
+ return;
+ case 3:
+ leaf->eax = 0x1C03C163;
+ leaf->ebx = 0x03C0003F;
+ leaf->ecx = 0x00001FFF;
+ leaf->edx = 0x00000006;
+ return;
+ default:
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+ }
+}
+
+// leaf 0x00000005 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_5(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000005 - MONITOR/MWAIT Leaf
+
+#if BX_SUPPORT_MONITOR_MWAIT
+ // EAX - Smallest monitor-line size in bytes
+ // EBX - Largest monitor-line size in bytes
+ // ECX -
+ // [31:2] - reserved
+ // [1:1] - exit MWAIT even with EFLAGS.IF = 0
+ // [0:0] - MONITOR/MWAIT extensions are supported
+ // EDX - Reserved
+ leaf->eax = CACHE_LINE_SIZE;
+ leaf->ebx = CACHE_LINE_SIZE;
+ leaf->ecx = 3;
+ leaf->edx = 0;
+#else
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+#endif
+}
+
+// leaf 0x00000006 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_6(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000006 - Thermal and Power Management Leaf
+ leaf->eax = 0x00000077;
+ leaf->ebx = 0x00000002;
+ leaf->ecx = 0x0000000B;
+ leaf->edx = 0x00000000;
+}
+
+// leaf 0x00000007 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_7(Bit32u subfunction, \
cpuid_function_t *leaf) +{
+ leaf->eax = 0; /* leaf 7 not supported */
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x00000008 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_8(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000008 - reserved
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x00000009 //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_9(cpuid_function_t *leaf)
+{
+ // CPUID function 0x00000009 - Direct Cache Access Information
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x0000000A //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_A(cpuid_function_t *leaf)
+{
+ // CPUID function 0x0000000A - Architectural Performance Monitoring Leaf
+ leaf->eax = 0x07300803;
+ leaf->ebx = 0x00000000;
+ leaf->ecx = 0x00000000;
+ leaf->edx = 0x00000603;
+
+ BX_INFO(("WARNING: Architectural Performance Monitoring is not implemented"));
+}
+
+BX_CPP_INLINE static Bit32u ilog2(Bit32u x)
+{
+ Bit32u count = 0;
+ while(x>>=1) count++;
+ return count;
+}
+
+// leaf 0x0000000B //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_extended_topology_leaf(Bit32u \
subfunction, cpuid_function_t *leaf) +{
+ // CPUID function 0x0000000B - Extended Topology Leaf
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = subfunction;
+ leaf->edx = cpu->get_apic_id();
+
+#if BX_SUPPORT_SMP
+ switch(subfunction) {
+ case 0:
+ if (nthreads > 1) {
+ leaf->eax = ilog2(nthreads-1)+1;
+ leaf->ebx = nthreads;
+ leaf->ecx |= (1<<8);
+ }
+ else if (ncores > 1) {
+ leaf->eax = ilog2(ncores-1)+1;
+ leaf->ebx = ncores;
+ leaf->ecx |= (2<<8);
+ }
+ else if (nprocessors > 1) {
+ leaf->eax = ilog2(nprocessors-1)+1;
+ leaf->ebx = nprocessors;
+ }
+ else {
+ leaf->eax = 1;
+ leaf->ebx = 1; // number of logical CPUs at this level
+ }
+ break;
+
+ case 1:
+ if (nthreads > 1) {
+ if (ncores > 1) {
+ leaf->eax = ilog2(ncores-1)+1;
+ leaf->ebx = ncores;
+ leaf->ecx |= (2<<8);
+ }
+ else if (nprocessors > 1) {
+ leaf->eax = ilog2(nprocessors-1)+1;
+ leaf->ebx = nprocessors;
+ }
+ }
+ else if (ncores > 1) {
+ if (nprocessors > 1) {
+ leaf->eax = ilog2(nprocessors-1)+1;
+ leaf->ebx = nprocessors;
+ }
+ }
+ break;
+
+ case 2:
+ if (nthreads > 1) {
+ if (nprocessors > 1) {
+ leaf->eax = ilog2(nprocessors-1)+1;
+ leaf->ebx = nprocessors;
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+#endif
+}
+
+// leaf 0x0000000C //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_leaf_C(cpuid_function_t *leaf)
+{
+ // CPUID function 0x0000000C - reserved
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+}
+
+// leaf 0x0000000D //
+void corei7_sandy_bridge_2600k_t::get_std_cpuid_xsave_leaf(Bit32u subfunction, \
cpuid_function_t *leaf) +{
+ if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE))
+ {
+ switch(subfunction) {
+ case 0:
+ // EAX - valid bits of XCR0 (lower part)
+ // EBX - Maximum size (in bytes) required by enabled features
+ // ECX - Maximum size (in bytes) required by CPU supported features
+ // EDX - valid bits of XCR0 (upper part)
+ leaf->eax = cpu->xcr0_suppmask;
+ leaf->ebx = 512+64;
+ if (cpu->xcr0_suppmask & BX_XCR0_AVX_MASK)
+ leaf->ebx += 256;
+ leaf->ecx = 512+64;
+ if (cpu->xcr0_suppmask & BX_XCR0_AVX_MASK)
+ leaf->ecx += 256;
+ leaf->edx = 0;
+ return;
+
+ case 1:
+ leaf->eax = BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVEOPT);
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+ return;
+
+ case 2: // AVX leaf
+ if (cpu->xcr0_suppmask & BX_XCR0_AVX_MASK) {
+ leaf->eax = 256;
+ leaf->ebx = 576;
+ leaf->ecx = 0;
+ leaf->edx = 0;
+ break;
+ }
+ // else fall through
+
+ default:
+ leaf->eax = 0; // reserved
+ leaf->ebx = 0; // reserved
+ leaf->ecx = 0; // reserved
+ leaf->edx = 0; // reserved
+ break;
+ }
+ }
+}
+
+// leaf 0x80000000 //
+void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf)
+{
+ // EAX: highest extended function understood by CPUID
+ // EBX: reserved
+ // EDX: reserved
+ // ECX: reserved
+ leaf->eax = 0x80000008;
+ leaf->ebx = 0;
+ leaf->edx = 0; // Reserved for Intel
+ leaf->ecx = 0;
+}
+
+// leaf 0x80000001 //
+void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf)
+{
+ // EAX: CPU Version Information (reserved for Intel)
+ leaf->eax = 0;
+
+ // EBX: Brand ID (reserved for Intel)
+ leaf->ebx = 0;
+
+ // ECX:
+ // * [0:0] LAHF/SAHF instructions support in 64-bit mode
+ // [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
+ // [2:2] SVM: Secure Virtual Machine (AMD)
+ // [3:3] Extended APIC Space
+ // [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
+ // [5:5] LZCNT: LZCNT instruction support
+ // [6:6] SSE4A: SSE4A Instructions support (deprecated?)
+ // [7:7] Misaligned SSE support
+ // [8:8] PREFETCHW: PREFETCHW instruction support
+ // [9:9] OSVW: OS visible workarounds (AMD)
+ // [11:10] reserved
+ // [12:12] SKINIT support
+ // [13:13] WDT: Watchdog timer support
+ // [31:14] reserved
+
+ leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF;
+
+ // EDX:
+ // Many of the bits in EDX are the same as EAX [*] for AMD
+ // [10:0] Reserved for Intel
+ // * [11:11] SYSCALL/SYSRET support
+ // [19:12] Reserved for Intel
+ // * [20:20] No-Execute page protection
+ // [25:21] Reserved
+ // [26:26] 1G paging support
+ // * [27:27] Support RDTSCP Instruction
+ // [28:28] Reserved
+ // * [29:29] Long Mode
+ // [30:30] AMD 3DNow! Extensions
+ // [31:31] AMD 3DNow! Instructions
+
+ leaf->edx = BX_CPUID_STD2_SYSCALL_SYSRET |
+ BX_CPUID_STD2_NX |
+ BX_CPUID_STD2_RDTSCP |
+ BX_CPUID_STD2_LONG_MODE;
+}
+
+// leaf 0x80000002 //
+// leaf 0x80000003 //
+// leaf 0x80000004 //
+void corei7_sandy_bridge_2600k_t::get_ext_cpuid_brand_string_leaf(Bit32u function, \
cpuid_function_t *leaf) +{
+ // CPUID function 0x800000002-0x800000004 - Processor Name String Identifier
+ static const char* brand_string = " Intel(R) Core(TM) i7-2600K CPU @ \
3.40GHz"; +
+ switch(function) {
+ case 0x80000002:
+ memcpy(&(leaf->eax), brand_string , 4);
+ memcpy(&(leaf->ebx), brand_string + 4, 4);
+ memcpy(&(leaf->ecx), brand_string + 8, 4);
+ memcpy(&(leaf->edx), brand_string + 12, 4);
+ break;
+ case 0x80000003:
+ memcpy(&(leaf->eax), brand_string + 16, 4);
+ memcpy(&(leaf->ebx), brand_string + 20, 4);
+ memcpy(&(leaf->ecx), brand_string + 24, 4);
+ memcpy(&(leaf->edx), brand_string + 28, 4);
+ break;
+ case 0x80000004:
+ memcpy(&(leaf->eax), brand_string + 32, 4);
+ memcpy(&(leaf->ebx), brand_string + 36, 4);
+ memcpy(&(leaf->ecx), brand_string + 40, 4);
+ memcpy(&(leaf->edx), brand_string + 44, 4);
+ break;
+ default:
+ break;
+ }
+
+#ifdef BX_BIG_ENDIAN
+ leaf->eax = bx_bswap32(leaf->eax);
+ leaf->ebx = bx_bswap32(leaf->ebx);
+ leaf->ecx = bx_bswap32(leaf->ecx);
+ leaf->edx = bx_bswap32(leaf->edx);
+#endif
+}
+
+// leaf 0x80000005 //
+void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_5(cpuid_function_t *leaf)
+{
+ // CPUID function 0x800000005 - L1 Cache and TLB Identifiers
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0; // reserved for Intel
+ leaf->edx = 0;
+}
+
+// leaf 0x80000006 //
+void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf)
+{
+ // CPUID function 0x800000006 - L2 Cache and TLB Identifiers
+ leaf->eax = 0x00000000;
+ leaf->ebx = 0x00000000;
+ leaf->ecx = 0x01006040;
+ leaf->edx = 0x00000000;
+}
+
+// leaf 0x80000007 //
+void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf)
+{
+ // CPUID function 0x800000007 - Advanced Power Management
+ leaf->eax = 0;
+ leaf->ebx = 0;
+ leaf->ecx = 0;
+ leaf->edx = 0x00000100; // bit 8 - invariant TSC
+}
+
+// leaf 0x80000008 //
+void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf)
+{
+ // virtual & phys address size in low 2 bytes.
+ leaf->eax = BX_PHY_ADDRESS_WIDTH | (BX_LIN_ADDRESS_WIDTH << 8);
+ leaf->ebx = 0;
+ leaf->ecx = 0; // Reserved, undefined
+ leaf->edx = 0;
+}
+
+void corei7_sandy_bridge_2600k_t::dump_cpuid(void)
+{
+ struct cpuid_function_t leaf;
+ unsigned n;
+
+ for (n=0; n<=0xd; n++) {
+ BX_CPU_THIS_PTR cpuid->get_cpuid_leaf(n, 0x00000000, &leaf);
+ BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, \
leaf.edx)); + }
+
+ for (n=0x80000000; n<=0x80000008; n++) {
+ BX_CPU_THIS_PTR cpuid->get_cpuid_leaf(n, 0x00000000, &leaf);
+ BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, \
leaf.edx)); + }
+}
+
+bx_cpuid_t *create_corei7_sandy_bridge_2600k_cpuid(BX_CPU_C *cpu) { return new \
corei7_sandy_bridge_2600k_t(cpu); } +
+#endif
Property changes on: trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc
___________________________________________________________________
Added: svn:executable
+ *
Added: svn:keywords
+ Author Date Id Rev
Added: trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.h
===================================================================
--- trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.h (rev 0)
+++ trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.h 2011-07-29 15:03:54 UTC (rev \
10505) @@ -0,0 +1,77 @@
+/////////////////////////////////////////////////////////////////////////
+// $Id$
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2011 Stanislav Shwartsman
+// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+//
+/////////////////////////////////////////////////////////////////////////
+
+#ifndef BX_GENERIC_CPUID_DEFINITIONS_H
+#define BX_GENERIC_CPUID_DEFINITIONS_H
+
+#include "cpu/cpuid.h"
+
+class corei7_sandy_bridge_2600k_t : public bx_cpuid_t {
+public:
+ corei7_sandy_bridge_2600k_t(BX_CPU_C *cpu);
+ virtual ~corei7_sandy_bridge_2600k_t() {}
+
+ // return CPU name
+ virtual const char *get_name(void) const { return "corei7_sandy_bridge_2600k"; }
+
+ virtual Bit32u get_isa_extensions_bitmask(void) const;
+ virtual Bit32u get_cpu_extensions_bitmask(void) const;
+
+ virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t \
*leaf); +
+ virtual void dump_cpuid(void);
+
+private:
+#if BX_SUPPORT_SMP
+ unsigned nprocessors;
+ unsigned ncores;
+ unsigned nthreads;
+#endif
+
+ void get_std_cpuid_leaf_0(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_1(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_2(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_3(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_5(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_6(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_7(Bit32u subfunction, cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_8(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_9(cpuid_function_t *leaf);
+ void get_std_cpuid_leaf_A(cpuid_function_t *leaf);
+ void get_std_cpuid_extended_topology_leaf(Bit32u subfunction, cpuid_function_t \
*leaf); + void get_std_cpuid_leaf_C(cpuid_function_t *leaf);
+ void get_std_cpuid_xsave_leaf(Bit32u subfunction, cpuid_function_t *leaf);
+
+ void get_ext_cpuid_leaf_0(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_1(cpuid_function_t *leaf);
+ void get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_5(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_6(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_7(cpuid_function_t *leaf);
+ void get_ext_cpuid_leaf_8(cpuid_function_t *leaf);
+};
+
+extern bx_cpuid_t *create_corei7_sandy_bridge_2600k_cpuid(BX_CPU_C *cpu);
+
+#endif
Property changes on: trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.h
___________________________________________________________________
Added: svn:executable
+ *
Added: svn:keywords
+ Author Date Id Rev
Added: trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.txt
===================================================================
--- trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.txt (rev \
0)
+++ trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.txt 2011-07-29 15:03:54 UTC (rev \
10505) @@ -0,0 +1,347 @@
+CPU-Z TXT Report
+-------------------------------------------------------------------------
+
+Binaries
+-------------------------------------------------------------------------
+
+CPU-Z version 1.58
+
+Processors
+-------------------------------------------------------------------------
+
+Number of processors 1
+Number of threads 4
+
+APICs
+-------------------------------------------------------------------------
+
+Processor 0
+ -- Core 0
+ -- Thread 0 0
+ -- Core 1
+ -- Thread 0 2
+ -- Core 2
+ -- Thread 0 4
+ -- Core 3
+ -- Thread 0 6
+
+Processors Information
+-------------------------------------------------------------------------
+
+Processor 1 ID = 0
+ Number of cores 4 (max 8)
+ Number of threads 4 (max 16)
+ Name Intel Core i7 2600K
+ Codename Sandy Bridge
+ Specification Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz (Engineering Sample)
+ Package (platform ID) Socket 1155 LGA (0x1)
+ CPUID 6.A.7
+ Extended CPUID 6.2A
+ Core Stepping D2
+ Technology 32 nm
+ TDP Limit 95 Watts
+ Core Speed 1596.3 MHz
+ Multiplier x FSB 16.0 x 99.8 MHz
+ Stock frequency 3400 MHz
+ Instructions sets MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, EM64T, VT-x, AES, \
AVX + L1 Data cache 4 x 32 KBytes, 8-way set associative, 64-byte line size
+ L1 Instruction cache 4 x 32 KBytes, 8-way set associative, 64-byte line size
+ L2 cache 4 x 256 KBytes, 8-way set associative, 64-byte line size
+ L3 cache 8 MBytes, 16-way set associative, 64-byte line size
+ FID/VID Control yes
+
+ Turbo Mode supported, enabled
+ Max non-turbo ratio 34x
+ Max turbo ratio 38x
+ Max efficiency ratio 16x
+ Max Power 120 Watts
+ Min Power 60 Watts
+ O/C bins unlimited
+
+
+Thread dumps
+-------------------------------------------------------------------------
+
+CPU Thread 0
+ APIC ID 0
+ Topology Processor ID 0, Core ID 0, Thread ID 0
+ Type 01400001h
+ Max CPUID level 0000000Dh
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 2 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 2 thread(s)
+ Cache descriptor Level 2, U, 256 KB, 2 thread(s)
+ Cache descriptor Level 3, U, 8 MB, 16 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000D 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x000206A7 0x00100800 0x1F9AE3BF 0xBFEBFBFF
+ 0x00000002 0x76035A01 0x00F0B0FF 0x00000000 0x00CA0000
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004122 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000
+ 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000006
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120
+ 0x00000006 0x00000077 0x00000002 0x0000000B 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07300803 0x00000000 0x00000000 0x00000603
+ 0x0000000B 0x00000001 0x00000002 0x00000100 0x00000000
+ 0x0000000B 0x00000004 0x00000008 0x00000201 0x00000000
+ 0x0000000C 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000D 0x00000007 0x00000340 0x00000340 0x00000000
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x28100800
+ 0x80000002 0x20202020 0x49202020 0x6C65746E 0x20295228
+ 0x80000003 0x65726F43 0x294D5428 0x2D376920 0x30303632
+ 0x80000004 0x5043204B 0x20402055 0x30342E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00900
+ MSR 0x0000003A 0x00000000 0x00000005
+ MSR 0x000001A0 0x00000000 0x08850089
+ MSR 0x000000CE 0x00001000 0x68012200
+ MSR 0x00000017 0x00040000 0x00000000
+ MSR 0x00000035 0x00000000 0x00040004
+ MSR 0x000000C1 0x00000000 0x00000000
+ MSR 0x000000C2 0x00000000 0x00000000
+ MSR 0x000000C3 0x00000000 0x00000000
+ MSR 0x000000C4 0x00000000 0x00000000
+ MSR 0x00000186 0x00000000 0x00000000
+ MSR 0x00000187 0x00000000 0x00000000
+ MSR 0x000001AD 0x00000000 0x23242526
+ MSR 0x00000194 0x00000000 0x000F0000
+ MSR 0x0000019A 0x00000000 0x00000000
+ MSR 0x000001A4 0x00000000 0x00000000
+ MSR 0x000001B1 0x00000000 0x88360000
+ MSR 0x000001FC 0x00000000 0x0004005F
+ MSR 0x00000601 0x18141494 0x0000030C
+ MSR 0x00000602 0x18141494 0x00000104
+ MSR 0x00000606 0x00000000 0x000A1003
+ MSR 0x00000610 0x000083B6 0x001482F8
+ MSR 0x00000611 0x00000000 0x149E2357
+ MSR 0x00000639 0x00000000 0x1D11FE3D
+ MSR 0x00000641 0x00000000 0xA710DDB9
+ MSR 0x00000614 0x000A03C0 0x01E002F8
+ MSR 0x0000019C 0x00000000 0x88360000
+ MSR 0x000001A2 0x00000000 0x00621400
+ MSR 0x00000198 0x00001F39 0x00001000
+ MSR 0x00000199 0x00000000 0x00001000
+
+CPU Thread 1
+ APIC ID 2
+ Topology Processor ID 0, Core ID 1, Thread ID 0
+ Type 01400001h
+ Max CPUID level 0000000Dh
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 2 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 2 thread(s)
+ Cache descriptor Level 2, U, 256 KB, 2 thread(s)
+ Cache descriptor Level 3, U, 8 MB, 16 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000D 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x000206A7 0x02100800 0x1F9AE3BF 0xBFEBFBFF
+ 0x00000002 0x76035A01 0x00F0B0FF 0x00000000 0x00CA0000
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004122 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000
+ 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000006
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120
+ 0x00000006 0x00000077 0x00000002 0x0000000B 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07300803 0x00000000 0x00000000 0x00000603
+ 0x0000000B 0x00000001 0x00000002 0x00000100 0x00000002
+ 0x0000000B 0x00000004 0x00000008 0x00000201 0x00000002
+ 0x0000000C 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000D 0x00000007 0x00000340 0x00000340 0x00000000
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x28100800
+ 0x80000002 0x20202020 0x49202020 0x6C65746E 0x20295228
+ 0x80000003 0x65726F43 0x294D5428 0x2D376920 0x30303632
+ 0x80000004 0x5043204B 0x20402055 0x30342E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00800
+ MSR 0x0000003A 0x00000000 0x00000005
+ MSR 0x000001A0 0x00000000 0x08850089
+ MSR 0x000000CE 0x00001000 0x68012200
+ MSR 0x00000017 0x00040000 0x00000000
+ MSR 0x00000035 0x00000000 0x00040004
+ MSR 0x000000C1 0x00000000 0x00000000
+ MSR 0x000000C2 0x00000000 0x00000000
+ MSR 0x000000C3 0x00000000 0x00000000
+ MSR 0x000000C4 0x00000000 0x00000000
+ MSR 0x00000186 0x00000000 0x00000000
+ MSR 0x00000187 0x00000000 0x00000000
+ MSR 0x000001AD 0x00000000 0x23242526
+ MSR 0x00000194 0x00000000 0x000F0000
+ MSR 0x0000019A 0x00000000 0x00000000
+ MSR 0x000001A4 0x00000000 0x00000000
+ MSR 0x000001B1 0x00000000 0x88370000
+ MSR 0x000001FC 0x00000000 0x0004005F
+ MSR 0x00000601 0x18141494 0x0000030C
+ MSR 0x00000602 0x18141494 0x00000104
+ MSR 0x00000606 0x00000000 0x000A1003
+ MSR 0x00000610 0x000083B6 0x001482F8
+ MSR 0x00000611 0x00000000 0x149E6AC0
+ MSR 0x00000639 0x00000000 0x1D120C3C
+ MSR 0x00000641 0x00000000 0xA710E264
+ MSR 0x00000614 0x000A03C0 0x01E002F8
+ MSR 0x0000019C 0x00000000 0x883D0000
+ MSR 0x000001A2 0x00000000 0x00621400
+ MSR 0x00000198 0x00001FDD 0x00001000
+ MSR 0x00000199 0x00000000 0x00001000
+
+CPU Thread 2
+ APIC ID 4
+ Topology Processor ID 0, Core ID 2, Thread ID 0
+ Type 01400001h
+ Max CPUID level 0000000Dh
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 2 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 2 thread(s)
+ Cache descriptor Level 2, U, 256 KB, 2 thread(s)
+ Cache descriptor Level 3, U, 8 MB, 16 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000D 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x000206A7 0x04100800 0x1F9AE3BF 0xBFEBFBFF
+ 0x00000002 0x76035A01 0x00F0B0FF 0x00000000 0x00CA0000
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004122 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000
+ 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000006
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120
+ 0x00000006 0x00000077 0x00000002 0x0000000B 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07300803 0x00000000 0x00000000 0x00000603
+ 0x0000000B 0x00000001 0x00000002 0x00000100 0x00000004
+ 0x0000000B 0x00000004 0x00000008 0x00000201 0x00000004
+ 0x0000000C 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000D 0x00000007 0x00000340 0x00000340 0x00000000
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x28100800
+ 0x80000002 0x20202020 0x49202020 0x6C65746E 0x20295228
+ 0x80000003 0x65726F43 0x294D5428 0x2D376920 0x30303632
+ 0x80000004 0x5043204B 0x20402055 0x30342E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00800
+ MSR 0x0000003A 0x00000000 0x00000005
+ MSR 0x000001A0 0x00000000 0x08850089
+ MSR 0x000000CE 0x00001000 0x68012200
+ MSR 0x00000017 0x00040000 0x00000000
+ MSR 0x00000035 0x00000000 0x00040004
+ MSR 0x000000C1 0x00000000 0x00000000
+ MSR 0x000000C2 0x00000000 0x00000000
+ MSR 0x000000C3 0x00000000 0x00000000
+ MSR 0x000000C4 0x00000000 0x00000000
+ MSR 0x00000186 0x00000000 0x00000000
+ MSR 0x00000187 0x00000000 0x00000000
+ MSR 0x000001AD 0x00000000 0x23242526
+ MSR 0x00000194 0x00000000 0x000F0000
+ MSR 0x0000019A 0x00000000 0x00000000
+ MSR 0x000001A4 0x00000000 0x00000000
+ MSR 0x000001B1 0x00000000 0x88370000
+ MSR 0x000001FC 0x00000000 0x0004005F
+ MSR 0x00000601 0x18141494 0x0000030C
+ MSR 0x00000602 0x18141494 0x00000104
+ MSR 0x00000606 0x00000000 0x000A1003
+ MSR 0x00000610 0x000083B6 0x001482F8
+ MSR 0x00000611 0x00000000 0x149EB54C
+ MSR 0x00000639 0x00000000 0x1D121D9A
+ MSR 0x00000641 0x00000000 0xA710E70C
+ MSR 0x00000614 0x000A03C0 0x01E002F8
+ MSR 0x0000019C 0x00000000 0x883B0000
+ MSR 0x000001A2 0x00000000 0x00621400
+ MSR 0x00000198 0x00001EE7 0x00001000
+ MSR 0x00000199 0x00000000 0x00001000
+
+CPU Thread 3
+ APIC ID 6
+ Topology Processor ID 0, Core ID 3, Thread ID 0
+ Type 01400001h
+ Max CPUID level 0000000Dh
+ Max CPUID ext. level 80000008h
+ Cache descriptor Level 1, D, 32 KB, 2 thread(s)
+ Cache descriptor Level 1, I, 32 KB, 2 thread(s)
+ Cache descriptor Level 2, U, 256 KB, 2 thread(s)
+ Cache descriptor Level 3, U, 8 MB, 16 thread(s)
+
+ CPUID
+ 0x00000000 0x0000000D 0x756E6547 0x6C65746E 0x49656E69
+ 0x00000001 0x000206A7 0x06100800 0x1F9AE3BF 0xBFEBFBFF
+ 0x00000002 0x76035A01 0x00F0B0FF 0x00000000 0x00CA0000
+ 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004122 0x01C0003F 0x0000003F 0x00000000
+ 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000
+ 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000006
+ 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120
+ 0x00000006 0x00000077 0x00000002 0x0000000B 0x00000000
+ 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000A 0x07300803 0x00000000 0x00000000 0x00000603
+ 0x0000000B 0x00000001 0x00000002 0x00000100 0x00000006
+ 0x0000000B 0x00000004 0x00000008 0x00000201 0x00000006
+ 0x0000000C 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0000000D 0x00000007 0x00000340 0x00000340 0x00000000
+ 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
+ 0x80000001 0x00000000 0x00000000 0x00000001 0x28100800
+ 0x80000002 0x20202020 0x49202020 0x6C65746E 0x20295228
+ 0x80000003 0x65726F43 0x294D5428 0x2D376920 0x30303632
+ 0x80000004 0x5043204B 0x20402055 0x30342E33 0x007A4847
+ 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000
+ 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100
+ 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000
+
+ MSR 0x0000001B 0x00000000 0xFEE00800
+ MSR 0x0000003A 0x00000000 0x00000005
+ MSR 0x000001A0 0x00000000 0x08850089
+ MSR 0x000000CE 0x00001000 0x68012200
+ MSR 0x00000017 0x00040000 0x00000000
+ MSR 0x00000035 0x00000000 0x00040004
+ MSR 0x000000C1 0x00000000 0x00000000
+ MSR 0x000000C2 0x00000000 0x00000000
+ MSR 0x000000C3 0x00000000 0x00000000
+ MSR 0x000000C4 0x00000000 0x00000000
+ MSR 0x00000186 0x00000000 0x00000000
+ MSR 0x00000187 0x00000000 0x00000000
+ MSR 0x000001AD 0x00000000 0x23242526
+ MSR 0x00000194 0x00000000 0x000F0000
+ MSR 0x0000019A 0x00000000 0x00000000
+ MSR 0x000001A4 0x00000000 0x00000000
+ MSR 0x000001B1 0x00000000 0x88370000
+ MSR 0x000001FC 0x00000000 0x0004005F
+ MSR 0x00000601 0x18141494 0x0000030C
+ MSR 0x00000602 0x18141494 0x00000104
+ MSR 0x00000606 0x00000000 0x000A1003
+ MSR 0x00000610 0x000083B6 0x001482F8
+ MSR 0x00000611 0x00000000 0x149F02B6
+ MSR 0x00000639 0x00000000 0x1D123295
+ MSR 0x00000641 0x00000000 0xA710EBC8
+ MSR 0x00000614 0x000A03C0 0x01E002F8
+ MSR 0x0000019C 0x00000000 0x883E0000
+ MSR 0x000001A2 0x00000000 0x00621400
+ MSR 0x00000198 0x00001F8B 0x00001000
+ MSR 0x00000199 0x00000000 0x00001000
Property changes on: trunk/bochs/cpu/cpudb/corei7_sandy_bridge_2600K.txt
___________________________________________________________________
Added: svn:executable
+ *
Added: trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc
===================================================================
--- trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc (rev 0)
+++ trunk/bochs/cpu/cpudb/p4_prescott_celeron_336.cc 2011-07-29 15:03:54 UTC (rev \
10505) @@ -0,0 +1,457 @@
+/////////////////////////////////////////////////////////////////////////
+// $Id$
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2011 Stanislav Shwartsman
+// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+//
+/////////////////////////////////////////////////////////////////////////
+
+#include "bochs.h"
+#include "cpu/cpu.h"
+#include "param_names.h"
+#include "p4_prescott_celeron_336.h"
+
+#define LOG_THIS cpu->
+
+#if BX_SUPPORT_X86_64
+
+p4_prescott_celeron_336_t::p4_prescott_celeron_336_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
+{
+#if BX_SUPPORT_SMP
+ nthreads = SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
+ ncores = SIM->get_param_num(BXPN_CPU_NCORES)->get();
+ nprocessors = SIM->get_param_num(BXPN_CPU_NPROCESSORS)->get();
+#endif
+
+ if (! BX_SUPPORT_X86_64)
+ BX_PANIC(("You must enable x86-64 for \"%s\" configuration"));
+}
+
+void p4_prescott_celeron_336_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, \
cpuid_function_t *leaf) +{
+ switch(function) {
+ case 0x80000000:
+ get_ext_cpuid_leaf_0(leaf);
+ return;
+ case 0x80000001:
+ get_ext_cpuid_leaf_1(leaf);
+ return;
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
+ get_ext_cpuid_brand_string_leaf(function, leaf);
+ return;
+ case 0x80000005:
+ get_ext_cpuid_leaf_5(leaf);
+ return;
+ case 0x80000006:
+ get_ext_cpuid_leaf_6(leaf);
+ return;
+ case 0x80000007:
+ get_ext_cpuid_leaf_7(leaf);
+ return;
+ case 0x80000008:
+ get_ext_cpuid_leaf_8(leaf);
+ return;
+ case 0x00000000:
+ get_std_cpuid_leaf_0(leaf);
+ return;
+ case 0x00000001:
+ get_std_cpuid_leaf_1(leaf);
+ return;
+ case 0x00000002:
+ get_std_cpuid_leaf_2(leaf);
+ return;
+ case 0x00000003:
+ default:
+ get_std_cpuid_leaf_3(leaf);
+ return;
+ }
+}
+
+Bit32u p4_prescott_celeron_336_t::get_isa_extensions_bitmask(void) const
+{
+ return BX_CPU_X87 |
+ BX_CPU_486 |
+ BX_CPU_PENTIUM |
+ BX_CPU_P6 |
+ BX_CPU_MMX |
+ BX_CPU_FXSAVE_FXRSTOR |
+ BX_CPU_SYSENTER_SYSEXIT |
+ BX_CPU_CLFLUSH |
+ BX_CPU_SSE |
+ BX_CPU_SSE2 |
+ BX_CPU_SSE3 |
+ BX_CPU_SSSE3 |
+#if BX_SUPPORT_MONITOR_MWAIT
+ BX_CPU_MONITOR_MWAIT |
+#endif
+ BX_CPU_X86_64;
+}
+
+Bit32u p4_prescott_celeron_336_t::get_cpu_extensions_bitmask(void) const
+{
+ return BX_CPU_DEBUG_EXTENSIONS |
+ BX_CPU_VME |
+ BX_CPU_PSE |
+ BX_CPU_PAE |
+ BX_CPU_PGE |
+ BX_CPU_PSE36 |
+ BX_CPU_PAT_MTRR |
+ BX_CPU_XAPIC;
+}
+
+// leaf 0x00000000 //
+void p4_prescott_celeron_336_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf)
+{
+ static const char* vendor_string = "GenuineIntel";
+
+ // EAX: highest std function understood by CPUID
+ // EBX: vendor ID string
+ // EDX: vendor ID string
+ // ECX: vendor ID string
+ leaf->eax = 0x3;
+
+ // CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
+ memcpy(&(leaf->ebx), vendor_string, 4);
+ memcpy(&(leaf->edx), vendor_string + 4, 4);
+ memcpy(&(leaf->ecx), vendor_string + 8, 4);
+#ifdef BX_BIG_ENDIAN
+ leaf->ebx = bx_bswap32(leaf->ebx);
+ leaf->ecx = bx_bswap32(leaf->ecx);
+ leaf->edx = bx_bswap32(leaf->edx);
+#endif
+}
+
+// leaf 0x00000001 //
+void p4_prescott_celeron_336_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf)
+{
+ // EAX: CPU Version Information
+ // [3:0] Stepping ID
+ // [7:4] Model: starts at 1
+ // [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
+ // [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
+ // [19:16] Extended Model
+ // [27:20] Extended Family
+ leaf->eax = 0x00000F41;
+
+ // EBX:
+ // [7:0] Brand ID
+ // [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
+ // [23:16] Number of logical processors in one physical processor
+ // [31:24] Local Apic ID
+
+ leaf->ebx = (CACHE_LINE_SIZE / 8) << 8;
+#if BX_SUPPORT_SMP
+ unsigned n_logical_processors = ncores*nthreads;
+ if (n_logical_processors > 1)
+ leaf->ebx |= (n_logical_processors << 16);
+#endif
+#if BX_SUPPORT_APIC
+ leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
+#endif
+
+ // ECX: Extended Feature Flags
+ // * [0:0] SSE3: SSE3 Instructions
+ // [1:1] PCLMULQDQ Instruction support
+ // * [2:2] DTES64: 64-bit DS area
+ // * [3:3] MONITOR/MWAIT support
+ // * [4:4] DS-CPL: CPL qualified debug store
+ // [5:5] VMX: Virtual Machine Technology
+ // [6:6] SMX: Secure Virtual Machine Technology
+ // [7:7] EST: Enhanced Intel SpeedStep Technology
+ // * [8:8] TM2: Thermal Monitor 2
+ // [9:9] SSSE3: SSSE3 Instructions
+ // * [10:10] CNXT-ID: L1 context ID
+ // [11:11] reserved
+ // [12:12] FMA Instructions support
+ // * [13:13] CMPXCHG16B: CMPXCHG16B instruction support
+ // * [14:14] xTPR update control
+ // [15:15] PDCM - Perfon and Debug Capability MSR
+ // [16:16] reserved
+ // [17:17] PCID: Process Context Identifiers
+ // [18:18] DCA - Direct Cache Access
+ // [19:19] SSE4.1 Instructions
+ // [20:20] SSE4.2 Instructions
+ // [21:21] X2APIC
+ // [22:22] MOVBE instruction
+ // [23:23] POPCNT instruction
+ // [24:24] TSC Deadline
+ // [25:25] AES Instructions
+ // [26:26] XSAVE extensions support
+ // [27:27] OSXSAVE support
+ // [28:28] AVX extensions support
+ // [29:29] AVX F16C - Float16 conversion support
+ // [30:30] RDRAND instruction
+ // [31:31] reserved
+ leaf->ecx = BX_CPUID_EXT_SSE3 |
+ BX_CPUID_EXT_DTES64 |
+#if BX_SUPPORT_MONITOR_MWAIT
+ BX_CPUID_EXT_MONITOR_MWAIT |
+#endif
+ BX_CPUID_EXT_DS_CPL |
+ BX_CPUID_EXT_THERMAL_MONITOR2 |
+ BX_CPUID_EXT_CNXT_ID |
+ BX_CPUID_EXT_CMPXCHG16B |
+ BX_CPUID_EXT_xTPR;
+
+ // EDX: Standard Feature Flags
@@ Diff output truncated at 100000 characters. @@
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