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List: bochs-cvs
Subject: [Bochs-cvs] CVS: bochs/cpu cpu.h, 1.607, 1.608 fetchdecode.cc, 1.227,
From: "Stanislav Shwartsman" <sshwarts () users ! sourceforge ! net>
Date: 2009-08-22 11:47:44
Message-ID: E1Mep4S-00028b-VT () ddv4jf1 ! ch3 ! sourceforge ! com
[Download RAW message or body]
Update of /cvsroot/bochs/bochs/cpu
In directory ddv4jf1.ch3.sourceforge.com:/tmp/cvs-serv8140
Modified Files:
cpu.h fetchdecode.cc fetchdecode64.cc fetchdecode.h
ia_opcodes.h sse_pfp.cc
Log Message:
split opcodes by ModC0
Index: cpu.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
retrieving revision 1.607
retrieving revision 1.608
diff -u -d -r1.607 -r1.608
--- cpu.h 10 Aug 2009 15:44:49 -0000 1.607
+++ cpu.h 22 Aug 2009 11:47:42 -0000 1.608
@@ -1953,8 +1953,10 @@
BX_SMF void MOVHPS_MqVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVAPS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVAPS_WpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
- BX_SMF void CVTPI2PS_VpsQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
- BX_SMF void CVTSI2SS_VssEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTPI2PS_VpsQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTPI2PS_VpsQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTSI2SS_VssEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTSI2SS_VssEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVNTPS_MpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTTPS2PI_PqWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTTSS2SI_GdWss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@@ -2004,8 +2006,10 @@
/* SSE2 */
BX_SMF void MOVSD_VsdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVSD_WsdVsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
- BX_SMF void CVTPI2PD_VpdQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
- BX_SMF void CVTSI2SD_VsdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTPI2PD_VpdQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTPI2PD_VpdQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
+ BX_SMF void CVTSI2SD_VsdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTTSD2SI_GdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
Index: fetchdecode.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode.cc,v
retrieving revision 1.227
retrieving revision 1.228
diff -u -d -r1.227 -r1.228
--- fetchdecode.cc 6 Apr 2009 18:44:28 -0000 1.227
+++ fetchdecode.cc 22 Aug 2009 11:47:42 -0000 1.228
@@ -536,7 +536,7 @@
/* 0F 27 /wr */ { 0, BX_IA_ERROR },
/* 0F 28 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
/* 0F 2B /wr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
/* 0F 2C /wr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /wr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -1099,7 +1099,7 @@
/* 0F 27 /dr */ { 0, BX_IA_ERROR },
/* 0F 28 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
/* 0F 2B /dr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
/* 0F 2C /dr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /dr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -1669,7 +1669,7 @@
/* 0F 27 /wm */ { 0, BX_IA_ERROR },
/* 0F 28 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
/* 0F 2B /wm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /wm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /wm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -2232,7 +2232,7 @@
/* 0F 27 /dm */ { 0, BX_IA_ERROR },
/* 0F 28 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
/* 0F 2B /dm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /dm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /dm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
Index: fetchdecode64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode64.cc,v
retrieving revision 1.230
retrieving revision 1.231
diff -u -d -r1.230 -r1.231
--- fetchdecode64.cc 6 Apr 2009 18:44:28 -0000 1.230
+++ fetchdecode64.cc 22 Aug 2009 11:47:42 -0000 1.231
@@ -484,7 +484,7 @@
/* 0F 27 /wr */ { 0, BX_IA_ERROR },
/* 0F 28 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
/* 0F 2B /wr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
/* 0F 2C /wr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /wr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -1011,7 +1011,7 @@
/* 0F 27 /dr */ { 0, BX_IA_ERROR },
/* 0F 28 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
/* 0F 2B /dr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
/* 0F 2C /dr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /dr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -1538,7 +1538,7 @@
/* 0F 27 /qr */ { 0, BX_IA_ERROR },
/* 0F 28 /qr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /qr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /qr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /qr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
/* 0F 2B /qr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
/* 0F 2C /qr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /qr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -2071,7 +2071,7 @@
/* 0F 27 /wm */ { 0, BX_IA_ERROR },
/* 0F 28 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
/* 0F 2B /wm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /wm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /wm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -2598,7 +2598,7 @@
/* 0F 27 /dm */ { 0, BX_IA_ERROR },
/* 0F 28 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
/* 0F 2B /dm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /dm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /dm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
@@ -3125,7 +3125,7 @@
/* 0F 27 /qm */ { 0, BX_IA_ERROR },
/* 0F 28 /qm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /qm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
- /* 0F 2A /qm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
+ /* 0F 2A /qm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
/* 0F 2B /qm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /qm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
/* 0F 2D /qm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
Index: fetchdecode.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode.h,v
retrieving revision 1.87
retrieving revision 1.88
diff -u -d -r1.87 -r1.88
--- fetchdecode.h 15 Aug 2009 15:43:40 -0000 1.87
+++ fetchdecode.h 22 Aug 2009 11:47:42 -0000 1.88
@@ -1072,10 +1072,16 @@
/* F3 */ { 0, BX_IA_ERROR }
};
-static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2a[3] = {
- /* 66 */ { 0, BX_IA_CVTPI2PD_VpdQq },
- /* F2 */ { 0, BX_IA_CVTSI2SD_VsdEd },
- /* F3 */ { 0, BX_IA_CVTSI2SS_VssEd }
+static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2aR[3] = {
+ /* 66 */ { 0, BX_IA_CVTPI2PD_VpdQqR },
+ /* F2 */ { 0, BX_IA_CVTSI2SD_VsdEdR },
+ /* F3 */ { 0, BX_IA_CVTSI2SS_VssEdR }
+};
+
+static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2aM[3] = {
+ /* 66 */ { 0, BX_IA_CVTPI2PD_VpdQqM },
+ /* F2 */ { 0, BX_IA_CVTSI2SD_VsdEdM },
+ /* F3 */ { 0, BX_IA_CVTSI2SS_VssEdM }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2bM[3] = {
Index: ia_opcodes.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/ia_opcodes.h,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -d -r1.27 -r1.28
--- ia_opcodes.h 6 Apr 2009 18:44:28 -0000 1.27
+++ ia_opcodes.h 22 Aug 2009 11:47:42 -0000 1.28
@@ -937,8 +937,10 @@
bx_define_opcode(BX_IA_MOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, NULL)
bx_define_opcode(BX_IA_MOVAPS_VpsWps, &BX_CPU_C::MOVAPS_VpsWps, NULL)
bx_define_opcode(BX_IA_MOVAPS_WpsVps, &BX_CPU_C::MOVAPS_WpsVps, NULL)
-bx_define_opcode(BX_IA_CVTPI2PS_VpsQq, &BX_CPU_C::CVTPI2PS_VpsQq, NULL)
-bx_define_opcode(BX_IA_CVTSI2SS_VssEd, &BX_CPU_C::CVTSI2SS_VssEd, NULL)
+bx_define_opcode(BX_IA_CVTPI2PS_VpsQqR, &BX_CPU_C::CVTPI2PS_VpsQqR, NULL)
+bx_define_opcode(BX_IA_CVTPI2PS_VpsQqM, &BX_CPU_C::CVTPI2PS_VpsQqM, NULL)
+bx_define_opcode(BX_IA_CVTSI2SS_VssEdR, &BX_CPU_C::CVTSI2SS_VssEdR, NULL)
+bx_define_opcode(BX_IA_CVTSI2SS_VssEdM, &BX_CPU_C::CVTSI2SS_VssEdM, NULL)
bx_define_opcode(BX_IA_MOVNTPS_MpsVps, &BX_CPU_C::MOVNTPS_MpsVps, NULL)
bx_define_opcode(BX_IA_CVTTPS2PI_PqWps, &BX_CPU_C::CVTTPS2PI_PqWps, NULL)
bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, &BX_CPU_C::CVTTSS2SI_GdWss, NULL)
@@ -988,8 +990,10 @@
// SSE2
bx_define_opcode(BX_IA_MOVSD_VsdWsd, &BX_CPU_C::MOVSD_VsdWsd, NULL)
bx_define_opcode(BX_IA_MOVSD_WsdVsd, &BX_CPU_C::MOVSD_WsdVsd, NULL)
-bx_define_opcode(BX_IA_CVTPI2PD_VpdQq, &BX_CPU_C::CVTPI2PD_VpdQq, NULL)
-bx_define_opcode(BX_IA_CVTSI2SD_VsdEd, &BX_CPU_C::CVTSI2SD_VsdEd, NULL)
+bx_define_opcode(BX_IA_CVTPI2PD_VpdQqR, &BX_CPU_C::CVTPI2PD_VpdQqR, NULL)
+bx_define_opcode(BX_IA_CVTPI2PD_VpdQqM, &BX_CPU_C::CVTPI2PD_VpdQqM, NULL)
+bx_define_opcode(BX_IA_CVTSI2SD_VsdEdR, &BX_CPU_C::CVTSI2SD_VsdEdR, NULL)
+bx_define_opcode(BX_IA_CVTSI2SD_VsdEdM, &BX_CPU_C::CVTSI2SD_VsdEdM, NULL)
bx_define_opcode(BX_IA_CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, NULL)
bx_define_opcode(BX_IA_CVTTSD2SI_GdWsd, &BX_CPU_C::CVTTSD2SI_GdWsd, NULL)
bx_define_opcode(BX_IA_CVTPD2PI_PqWpd, &BX_CPU_C::CVTPD2PI_PqWpd, NULL)
Index: sse_pfp.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/sse_pfp.cc,v
retrieving revision 1.60
retrieving revision 1.61
diff -u -d -r1.60 -r1.61
--- sse_pfp.cc 22 Aug 2009 11:02:45 -0000 1.60
+++ sse_pfp.cc 22 Aug 2009 11:47:42 -0000 1.61
@@ -83,7 +83,34 @@
* to rounding control bits in MXCSR register.
* Possible floating point exceptions: #P
*/
-void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqR(bxInstruction_c *i)
+{
+#if BX_SUPPORT_SSE >= 1
+ BX_CPU_THIS_PTR prepareSSE();
+
+ BxPackedXmmRegister result;
+
+ /* check floating point status word for a pending FPU exceptions */
+ FPU_check_pending_exceptions();
+
+ BxPackedMmxRegister op = BX_READ_MMX_REG(i->rm());
+
+ float_status_t status_word;
+ mxcsr_to_softfloat_status_word(status_word, MXCSR);
+
+ result.xmm32u(0) = int32_to_float32(MMXUD0(op), status_word);
+ result.xmm32u(1) = int32_to_float32(MMXUD1(op), status_word);
+
+ check_exceptionsSSE(status_word.float_exception_flags);
+ prepareFPU2MMX(); /* cause FPU2MMX state transition */
+ BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result.xmm64u(0));
+#else
+ BX_INFO(("CVTPI2PS_VpsQq: required SSE, use --enable-sse option"));
+ exception(BX_UD_EXCEPTION, 0, 0);
+#endif
+}
+
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqM(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareSSE();
@@ -91,19 +118,9 @@
BxPackedMmxRegister op;
BxPackedXmmRegister result;
- /* op is a register or memory reference */
- if (i->modC0()) {
- /* check floating point status word for a pending FPU exceptions */
- FPU_check_pending_exceptions();
- op = BX_READ_MMX_REG(i->rm());
- prepareFPU2MMX(); /* cause FPU2MMX state transition */
- }
- else {
- // do not cause transition to MMX state if no MMX register touched
- bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
- /* pointer, segment address pair */
- MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
- }
+ // do not cause transition to MMX state if no MMX register touched
+ bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
+ MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
float_status_t status_word;
mxcsr_to_softfloat_status_word(status_word, MXCSR);
@@ -124,7 +141,30 @@
* Convert two 32bit signed integers from MMX/MEM to two double precision FP
* Possible floating point exceptions: -
*/
-void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQq(bxInstruction_c *i)
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqR(bxInstruction_c *i)
+{
+#if BX_SUPPORT_SSE >= 2
+ BX_CPU_THIS_PTR prepareSSE();
+
+ BxPackedXmmRegister result;
+
+ /* check floating point status word for a pending FPU exceptions */
+ FPU_check_pending_exceptions();
+ prepareFPU2MMX(); /* cause FPU2MMX state transition */
+
+ BxPackedMmxRegister op = BX_READ_MMX_REG(i->rm());
+
+ result.xmm64u(0) = int32_to_float64(MMXUD0(op));
+ result.xmm64u(1) = int32_to_float64(MMXUD1(op));
+
+ BX_WRITE_XMM_REG(i->nnn(), result);
+#else
+ BX_INFO(("CVTPI2PD_VpdQd: required SSE2, use --enable-sse option"));
+ exception(BX_UD_EXCEPTION, 0, 0);
+#endif
+}
+
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqM(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
BX_CPU_THIS_PTR prepareSSE();
@@ -132,19 +172,9 @@
BxPackedMmxRegister op;
BxPackedXmmRegister result;
- /* op is a register or memory reference */
- if (i->modC0()) {
- /* check floating point status word for a pending FPU exceptions */
- FPU_check_pending_exceptions();
- op = BX_READ_MMX_REG(i->rm());
- prepareFPU2MMX(); /* cause FPU2MMX state transition */
- }
- else {
- // do not cause transition to MMX state if no MMX register touched
- bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
- /* pointer, segment address pair */
- MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
- }
+ // do not cause transition to MMX state if no MMX register touched
+ bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
+ MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
result.xmm64u(0) = int32_to_float64(MMXUD0(op));
result.xmm64u(1) = int32_to_float64(MMXUD1(op));
@@ -161,7 +191,7 @@
* Convert one 32bit signed integer to one double precision FP
* Possible floating point exceptions: -
*/
-void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEdR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
BX_CPU_THIS_PTR prepareSSE();
@@ -171,37 +201,41 @@
float64 result;
#if BX_SUPPORT_X86_64
- if (i->os64L()) /* 64 bit operand size mode */
- {
- Bit64u op;
+ if (i->os64L()) /* 64 bit operand size */
+ result = int64_to_float64(BX_READ_64BIT_REG(i->rm()), status_word);
+ else
+#endif
+ result = int32_to_float64(BX_READ_32BIT_REG(i->rm()));
- /* op is a register or memory reference */
- if (i->modC0()) {
- op = BX_READ_64BIT_REG(i->rm());
- }
- else {
- bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
- /* pointer, segment address pair */
- op = read_virtual_qword_64(i->seg(), eaddr);
- }
+ check_exceptionsSSE(status_word.float_exception_flags);
+ BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
+#else
+ BX_INFO(("CVTSI2SD_VsdEd: required SSE2, use --enable-sse option"));
+ exception(BX_UD_EXCEPTION, 0, 0);
+#endif
+}
+
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEdM(bxInstruction_c *i)
+{
+#if BX_SUPPORT_SSE >= 2
+ BX_CPU_THIS_PTR prepareSSE();
+
+ float_status_t status_word;
+ mxcsr_to_softfloat_status_word(status_word, MXCSR);
+ float64 result;
+ bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
+
+#if BX_SUPPORT_X86_64
+ if (i->os64L()) /* 64 bit operand size */
+ {
+ Bit64u op = read_virtual_qword_64(i->seg(), eaddr);
result = int64_to_float64(op, status_word);
}
else
#endif
{
- Bit32u op;
-
- /* op is a register or memory reference */
- if (i->modC0()) {
- op = BX_READ_32BIT_REG(i->rm());
- }
- else {
- bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
- /* pointer, segment address pair */
- op = read_virtual_dword(i->seg(), eaddr);
- }
-
+ Bit32u op = read_virtual_dword(i->seg(), eaddr);
result = int32_to_float64(op);
}
@@ -220,7 +254,7 @@
* to rounding control bits in MXCSR register.
* Possible floating point exceptions: #P
*/
-void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEdR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareSSE();
@@ -230,37 +264,41 @@
float32 result;
#if BX_SUPPORT_X86_64
- if (i->os64L()) /* 64 bit operand size mode */
- {
- Bit64u op;
+ if (i->os64L()) /* 64 bit operand size */
+ result = int64_to_float32(BX_READ_64BIT_REG(i->rm()), status_word);
+ else
+#endif
+ result = int32_to_float32(BX_READ_32BIT_REG(i->rm()), status_word);
- /* op is a register or memory reference */
- if (i->modC0()) {
- op = BX_READ_64BIT_REG(i->rm());
- }
- else {
- bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
- /* pointer, segment address pair */
- op = read_virtual_qword_64(i->seg(), eaddr);
- }
+ check_exceptionsSSE(status_word.float_exception_flags);
+ BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
+#else
+ BX_INFO(("CVTSI2SS_VssEd: required SSE, use --enable-sse option"));
+ exception(BX_UD_EXCEPTION, 0, 0);
+#endif
+}
+
+void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEdM(bxInstruction_c *i)
+{
+#if BX_SUPPORT_SSE >= 1
+ BX_CPU_THIS_PTR prepareSSE();
+
+ float_status_t status_word;
+ mxcsr_to_softfloat_status_word(status_word, MXCSR);
+ float32 result;
+
+ bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
+#if BX_SUPPORT_X86_64
+ if (i->os64L()) /* 64 bit operand size */
+ {
+ Bit64u op = read_virtual_qword_64(i->seg(), eaddr);
result = int64_to_float32(op, status_word);
}
else
#endif
{
- Bit32u op;
-
- /* op is a register or memory reference */
- if (i->modC0()) {
- op = BX_READ_32BIT_REG(i->rm());
- }
- else {
- bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
- /* pointer, segment address pair */
- op = read_virtual_dword(i->seg(), eaddr);
- }
-
+ Bit32u op = read_virtual_dword(i->seg(), eaddr);
result = int32_to_float32(op, status_word);
}
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