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List: bochs-cvs
Subject: [Bochs-cvs] CVS: bochs/cpu cpu.cc, 1.182, 1.183 cpu.h, 1.374,
From: Stanislav Shwartsman <sshwarts () users ! sourceforge ! net>
Date: 2007-11-24 14:22:38
Message-ID: E1Ivvu2-0001h7-Hf () sc8-pr-cvs3 ! sourceforge ! net
[Download RAW message or body]
Update of /cvsroot/bochs/bochs/cpu
In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv6068/cpu
Modified Files:
cpu.cc cpu.h ctrl_xfer16.cc ctrl_xfer32.cc ctrl_xfer64.cc
debugstuff.cc exception.cc fetchdecode64.cc flag_ctrl.cc
init.cc iret.cc resolve64.cc segment_ctrl_pro.cc smm.cc
soft_int.cc stack16.cc stack32.cc stack64.cc stack_pro.cc
tasking.cc
Log Message:
Eliminate saving of RSP from heart of cpu_loop
Now save RSP only where it is really required
Index: cpu.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpu.cc,v
retrieving revision 1.182
retrieving revision 1.183
diff -u -d -r1.182 -r1.183
--- cpu.cc 17 Nov 2007 23:28:30 -0000 1.182
+++ cpu.cc 24 Nov 2007 14:22:32 -0000 1.183
@@ -220,8 +220,8 @@
// back from an exception() call. In either case, commit the
// new EIP/ESP, and set up other environmental fields. This code
// mirrors similar code below, after the interrupt() call.
- BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
- BX_CPU_THIS_PTR prev_esp = RSP; // commit new ESP
+ BX_CPU_THIS_PTR prev_rip = RIP; // commit new EIP
+ BX_CPU_THIS_PTR speculative_rsp = 0;
BX_CPU_THIS_PTR EXT = 0;
BX_CPU_THIS_PTR errorno = 0;
@@ -263,7 +263,7 @@
#if BX_DEBUGGER
bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
#else
- debug_disasm_instruction(BX_CPU_THIS_PTR prev_eip);
+ debug_disasm_instruction(BX_CPU_THIS_PTR prev_rip);
#endif
}
#endif
@@ -272,8 +272,7 @@
BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
RIP += i->ilen();
BX_CPU_CALL_METHOD(i->execute, (i)); // might iterate repeat instruction
- BX_CPU_THIS_PTR prev_eip = RIP; // commit new RIP
- BX_CPU_THIS_PTR prev_esp = RSP; // commit new RSP
+ BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
BX_TICK1_IF_SINGLE_PROCESSOR();
@@ -353,7 +352,7 @@
}
}
- RIP = BX_CPU_THIS_PTR prev_eip; // repeat loop not done, restore RIP
+ RIP = BX_CPU_THIS_PTR prev_rip; // repeat loop not done, restore RIP
}
void BX_CPU_C::repeat_ZFL(bxInstruction_c *i, BxExecutePtr_t execute)
@@ -428,7 +427,7 @@
}
}
- RIP = BX_CPU_THIS_PTR prev_eip; // repeat loop not done, restore RIP
+ RIP = BX_CPU_THIS_PTR prev_rip; // repeat loop not done, restore RIP
}
unsigned BX_CPU_C::handleAsyncEvent(void)
@@ -575,8 +574,8 @@
// the new EIP/ESP values. But here, we call interrupt() much like
// it was a sofware interrupt instruction, and need to effect the
// commit here. This code mirrors similar code above.
- BX_CPU_THIS_PTR prev_eip = RIP; // commit new RIP
- BX_CPU_THIS_PTR prev_esp = RSP; // commit new RSP
+ BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
+ BX_CPU_THIS_PTR speculative_rsp = 0;
BX_CPU_THIS_PTR EXT = 0;
BX_CPU_THIS_PTR errorno = 0;
}
@@ -627,7 +626,7 @@
else {
// only bother comparing if any breakpoints enabled
if (BX_CPU_THIS_PTR dr7 & 0x000000ff) {
- bx_address iaddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + BX_CPU_THIS_PTR prev_eip;
+ bx_address iaddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + BX_CPU_THIS_PTR prev_rip;
Bit32u dr6_bits = hwdebug_compare(iaddr, 1, BX_HWDebugInstruction, BX_HWDebugInstruction);
if (dr6_bits)
{
@@ -785,7 +784,7 @@
}
// Restore EIP since we fudged it to start at the 2nd page boundary.
- RIP = BX_CPU_THIS_PTR prev_eip;
+ RIP = BX_CPU_THIS_PTR prev_rip;
// Since we cross an instruction boundary, note that we need a prefetch()
// again on the next instruction. Perhaps we can optimize this to
Index: cpu.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
retrieving revision 1.374
retrieving revision 1.375
diff -u -d -r1.374 -r1.375
--- cpu.h 23 Nov 2007 22:49:54 -0000 1.374
+++ cpu.h 24 Nov 2007 14:22:32 -0000 1.375
@@ -440,23 +440,29 @@
(BX_CPU_THIS_PTR eflags.val32&~(1<<bitnum))|((val)<<bitnum); \
}
-#if BX_SUPPORT_ALIGNMENT_CHECK
+#if BX_SUPPORT_ALIGNMENT_CHECK && BX_CPU_LEVEL >= 4
#define DECLARE_EFLAG_ACCESSOR_AC(bitnum) \
- BX_CPP_INLINE void clear_AC (); \
+ BX_CPP_INLINE void clear_AC(); \
BX_CPP_INLINE Bit32u get_AC(); \
BX_CPP_INLINE bx_bool getB_AC(); \
+ BX_CPP_INLINE void set_AC(bx_bool val); \
#define IMPLEMENT_EFLAG_ACCESSOR_AC(bitnum) \
BX_CPP_INLINE void BX_CPU_C::clear_AC () { \
BX_CPU_THIS_PTR eflags.val32 &= ~(1<<bitnum); \
BX_CPU_THIS_PTR alignment_check = 0; \
} \
- BX_CPP_INLINE Bit32u BX_CPU_C::get_AC() { \
+ BX_CPP_INLINE Bit32u BX_CPU_C::get_AC() { \
return BX_CPU_THIS_PTR eflags.val32 & (1 << bitnum); \
} \
- BX_CPP_INLINE Bit32u BX_CPU_C::getB_AC() { \
+ BX_CPP_INLINE Bit32u BX_CPU_C::getB_AC() { \
return 1 & (BX_CPU_THIS_PTR eflags.val32 >> bitnum); \
+ } \
+ BX_CPP_INLINE void BX_CPU_C::set_AC(bx_bool val) { \
+ BX_CPU_THIS_PTR eflags.val32 = \
+ (BX_CPU_THIS_PTR eflags.val32&~(1<<bitnum))|((val)<<bitnum); \
+ handleAlignmentCheck(); \
}
#endif
@@ -1099,8 +1105,9 @@
// so that we can back up when handling faults, exceptions, etc.
// we need to store the value of the instruction pointer, before
// each fetch/execute cycle.
- bx_address prev_eip;
- bx_address prev_esp;
+ bx_address prev_rip;
+ bx_address prev_rsp;
+ bx_bool speculative_rsp;
#define BX_INHIBIT_INTERRUPTS 0x01
#define BX_INHIBIT_DEBUG 0x02
@@ -3276,7 +3283,7 @@
DECLARE_EFLAG_ACCESSOR (ID, 21)
DECLARE_EFLAG_ACCESSOR (VIP, 20)
DECLARE_EFLAG_ACCESSOR (VIF, 19)
-#if BX_SUPPORT_ALIGNMENT_CHECK
+#if BX_SUPPORT_ALIGNMENT_CHECK && BX_CPU_LEVEL >= 4
DECLARE_EFLAG_ACCESSOR_AC( 18)
#else
DECLARE_EFLAG_ACCESSOR (AC, 18)
Index: ctrl_xfer16.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/ctrl_xfer16.cc,v
retrieving revision 1.42
retrieving revision 1.43
diff -u -d -r1.42 -r1.43
--- ctrl_xfer16.cc 18 Nov 2007 18:24:45 -0000 1.42
+++ ctrl_xfer16.cc 24 Nov 2007 14:22:33 -0000 1.43
@@ -31,6 +31,11 @@
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
+// Make code more tidy with a few macros.
+#if BX_SUPPORT_X86_64==0
+#define RSP ESP
+#endif
+
void BX_CPU_C::RETnear16_Iw(bxInstruction_c *i)
{
@@ -40,6 +45,9 @@
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&return_IP);
if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
@@ -55,7 +63,9 @@
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
ESP += imm16;
else
- SP += imm16;
+ SP += imm16;
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
}
@@ -68,6 +78,9 @@
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&return_IP);
if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
@@ -78,6 +91,8 @@
EIP = return_IP;
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
}
@@ -94,12 +109,13 @@
imm16 = i->Iw();
-#if BX_CPU_LEVEL >= 2
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (protected_mode()) {
BX_CPU_THIS_PTR return_protected(i, imm16);
goto done;
}
-#endif
pop_16(&ip);
pop_16(&cs_raw);
@@ -110,9 +126,12 @@
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
ESP += imm16;
else
- SP += imm16;
+ SP += imm16;
done:
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -127,12 +146,13 @@
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
-#if BX_CPU_LEVEL >= 2
- if ( protected_mode() ) {
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ if (protected_mode()) {
BX_CPU_THIS_PTR return_protected(i, 0);
goto done;
}
-#endif
pop_16(&ip);
pop_16(&cs_raw);
@@ -141,6 +161,9 @@
EIP = (Bit32u) ip;
done:
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -183,12 +206,13 @@
disp16 = i->Iw();
cs_raw = i->Iw2();
-#if BX_CPU_LEVEL >= 2
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (protected_mode()) {
BX_CPU_THIS_PTR call_protected(i, cs_raw, disp16);
goto done;
}
-#endif
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_16((Bit16u) EIP);
@@ -197,6 +221,9 @@
EIP = (Bit32u) disp16;
done:
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -216,13 +243,11 @@
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
-#if BX_CPU_LEVEL >= 2
if (op1_16 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
{
BX_ERROR(("CALL_Ew: IP out of CS limits!"));
exception(BX_GP_EXCEPTION, 0, 0);
}
-#endif
push_16(IP);
EIP = op1_16;
@@ -244,6 +269,9 @@
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
read_virtual_word(i->seg(), RMAddr(i)+2, &cs_raw);
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (protected_mode()) {
BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_16);
goto done;
@@ -256,6 +284,9 @@
EIP = op1_16;
done:
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -535,17 +566,20 @@
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
read_virtual_word(i->seg(), RMAddr(i)+2, &cs_raw);
-#if BX_CPU_LEVEL >= 2
- if ( protected_mode() ) {
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ if (protected_mode()) {
BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_16);
goto done;
}
-#endif
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
EIP = op1_16;
done:
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -562,6 +596,9 @@
BX_CPU_THIS_PTR nmi_disable = 0;
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (v8086_mode()) {
// IOPL check in stack_return_from_v86()
iret16_stack_return_from_v86(i);
@@ -587,6 +624,8 @@
write_flags(flags, /* change IOPL? */ 1, /* change IF? */ 1);
done:
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
Index: ctrl_xfer32.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/ctrl_xfer32.cc,v
retrieving revision 1.54
retrieving revision 1.55
diff -u -d -r1.54 -r1.55
--- ctrl_xfer32.cc 17 Nov 2007 18:08:46 -0000 1.54
+++ ctrl_xfer32.cc 24 Nov 2007 14:22:33 -0000 1.55
@@ -31,6 +31,10 @@
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
+// Make code more tidy with a few macros.
+#if BX_SUPPORT_X86_64==0
+#define RSP ESP
+#endif
#if BX_CPU_LEVEL >= 3
@@ -42,13 +46,18 @@
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
Bit16u imm16 = i->Iw();
pop_32(&return_EIP);
branch_near32(return_EIP);
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
ESP += imm16;
else
- SP += imm16;
+ SP += imm16;
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
}
@@ -61,9 +70,14 @@
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_32(&return_EIP);
branch_near32(return_EIP);
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
}
@@ -79,6 +93,9 @@
Bit16u imm16 = i->Iw();
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (protected_mode()) {
BX_CPU_THIS_PTR return_protected(i, imm16);
goto done;
@@ -93,9 +110,11 @@
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
ESP += imm16;
else
- SP += imm16;
+ SP += imm16;
done:
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -110,7 +129,10 @@
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
- if ( protected_mode() ) {
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ if (protected_mode()) {
BX_CPU_THIS_PTR return_protected(i, 0);
goto done;
}
@@ -122,6 +144,8 @@
EIP = eip;
done:
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -160,6 +184,9 @@
disp32 = i->Id();
cs_raw = i->Iw2();
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (protected_mode()) {
BX_CPU_THIS_PTR call_protected(i, cs_raw, disp32);
goto done;
@@ -172,6 +199,8 @@
EIP = disp32;
done:
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -218,7 +247,10 @@
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
- if ( protected_mode() ) {
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ if (protected_mode()) {
BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_32);
goto done;
}
@@ -230,6 +262,8 @@
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
done:
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -480,6 +514,9 @@
}
cs_raw = i->Iw2();
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (protected_mode()) {
BX_CPU_THIS_PTR jump_protected(i, cs_raw, disp32);
}
@@ -488,6 +525,8 @@
EIP = disp32;
}
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -522,6 +561,9 @@
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (protected_mode()) {
BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_32);
}
@@ -530,6 +572,8 @@
EIP = op1_32;
}
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
@@ -544,6 +588,9 @@
BX_CPU_THIS_PTR nmi_disable = 0;
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (v8086_mode()) {
// IOPL check in stack_return_from_v86()
iret32_stack_return_from_v86(i);
@@ -579,6 +626,8 @@
writeEFlags(eflags, 0x00257fd5); // VIF, VIP, VM unchanged
done:
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
}
Index: ctrl_xfer64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/ctrl_xfer64.cc,v
retrieving revision 1.53
retrieving revision 1.54
diff -u -d -r1.53 -r1.54
--- ctrl_xfer64.cc 17 Nov 2007 12:44:09 -0000 1.53
+++ ctrl_xfer64.cc 24 Nov 2007 14:22:33 -0000 1.54
@@ -44,6 +44,9 @@
Bit16u imm16 = i->Iw();
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_64(&return_RIP);
if (! IsCanonical(return_RIP)) {
@@ -54,6 +57,8 @@
RIP = return_RIP;
RSP += imm16;
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, RIP);
}
@@ -65,6 +70,9 @@
BX_CPU_THIS_PTR show_flag |= Flag_ret;
#endif
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_64(&return_RIP);
if (! IsCanonical(return_RIP)) {
@@ -74,6 +82,8 @@
RIP = return_RIP;
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, RIP);
}
@@ -87,10 +97,14 @@
BX_ASSERT(protected_mode());
- BX_INFO(("RETfar64_Iw instruction executed ..."));
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+ // return_protected is not RSP safe
return_protected(i, i->Iw());
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
}
@@ -105,10 +119,14 @@
BX_ASSERT(protected_mode());
- BX_INFO(("RETfar64 instruction executed ..."));
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+ // return_protected is not RSP safe
return_protected(i, 0);
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
}
@@ -177,7 +195,13 @@
BX_ASSERT(protected_mode());
- BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_32);
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ // call_protected is not RSP safe
+ call_protected(i, cs_raw, op1_32);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
@@ -430,7 +454,14 @@
read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
BX_ASSERT(protected_mode());
- BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_32);
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ // jump_protected is nto RSP safe
+ jump_protected(i, cs_raw, op1_32);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
@@ -447,7 +478,14 @@
BX_CPU_THIS_PTR nmi_disable = 0;
BX_ASSERT(protected_mode());
- iret_protected(i);
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ // long_iret is not RSP safe
+ long_iret(i);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
Index: debugstuff.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/debugstuff.cc,v
retrieving revision 1.85
retrieving revision 1.86
diff -u -d -r1.85 -r1.86
--- debugstuff.cc 8 Nov 2007 18:21:37 -0000 1.85
+++ debugstuff.cc 24 Nov 2007 14:22:33 -0000 1.86
@@ -238,8 +238,8 @@
#if BX_SUPPORT_X86_64
BX_INFO(("| RIP=%08x%08x (%08x%08x)",
(unsigned) BX_CPU_THIS_PTR eip_reg.dword.rip_upper, (unsigned) EIP,
- (unsigned) (BX_CPU_THIS_PTR prev_eip >> 32),
- (unsigned) (BX_CPU_THIS_PTR prev_eip & 0xffffffff)));
+ (unsigned) (BX_CPU_THIS_PTR prev_rip >> 32),
+ (unsigned) (BX_CPU_THIS_PTR prev_rip & 0xffffffff)));
BX_INFO(("| CR0=0x%08x CR1=0x%x CR2=0x%08x%08x",
(unsigned) (BX_CPU_THIS_PTR cr0.val32), 0,
(unsigned) (BX_CPU_THIS_PTR cr2 >> 32),
@@ -248,7 +248,7 @@
(unsigned) BX_CPU_THIS_PTR cr3, BX_CPU_THIS_PTR cr4.getRegister()));
#else
BX_INFO(("| EIP=%08x (%08x)", (unsigned) EIP,
- (unsigned) BX_CPU_THIS_PTR prev_eip));
+ (unsigned) BX_CPU_THIS_PTR prev_rip));
#if BX_CPU_LEVEL >= 2 && BX_CPU_LEVEL < 4
BX_INFO(("| CR0=0x%08x CR1=%x CR2=0x%08x CR3=0x%08x",
@@ -440,5 +440,5 @@
void BX_CPU_C::atexit(void)
{
- debug(BX_CPU_THIS_PTR prev_eip);
+ debug(BX_CPU_THIS_PTR prev_rip);
}
Index: exception.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/exception.cc,v
retrieving revision 1.95
retrieving revision 1.96
diff -u -d -r1.95 -r1.96
--- exception.cc 6 Nov 2007 19:17:42 -0000 1.95
+++ exception.cc 24 Nov 2007 14:22:33 -0000 1.96
@@ -851,7 +851,7 @@
// if 1st was a double fault (software INT?), then shutdown
(BX_CPU_THIS_PTR errorno == 2 && BX_CPU_THIS_PTR curr_exception[0]==BX_ET_DOUBLE_FAULT))
{
- debug(BX_CPU_THIS_PTR prev_eip); // print debug information to the log
+ debug(BX_CPU_THIS_PTR prev_rip); // print debug information to the log
#if BX_DEBUGGER
// trap into debugger (similar as done when PANIC occured)
bx_debug_break();
@@ -998,8 +998,9 @@
if (exception_class == BX_EXCEPTION_CLASS_FAULT)
{
// restore RIP/RSP to value before error occurred
- RIP = BX_CPU_THIS_PTR prev_eip;
- RSP = BX_CPU_THIS_PTR prev_esp;
+ RIP = BX_CPU_THIS_PTR prev_rip;
+ if (BX_CPU_THIS_PTR speculative_rsp)
+ RSP = BX_CPU_THIS_PTR prev_rsp;
if (vector != BX_DB_EXCEPTION) BX_CPU_THIS_PTR assert_RF();
}
Index: fetchdecode64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode64.cc,v
retrieving revision 1.147
retrieving revision 1.148
diff -u -d -r1.147 -r1.148
--- fetchdecode64.cc 23 Nov 2007 16:37:06 -0000 1.147
+++ fetchdecode64.cc 24 Nov 2007 14:22:33 -0000 1.148
@@ -909,7 +909,7 @@
/* CC /dr */ { 0, &BX_CPU_C::INT3 },
/* CD /dr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
/* CE /dr */ { 0, &BX_CPU_C::BxError },
- /* CF /dr */ { 0, &BX_CPU_C::IRET32 },
+ /* CF /dr */ { 0, &BX_CPU_C::IRET64 },
/* D0 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
/* D1 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
/* D2 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
@@ -1973,7 +1973,7 @@
/* CC /wm */ { 0, &BX_CPU_C::INT3 },
/* CD /wm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
/* CE /wm */ { 0, &BX_CPU_C::BxError },
- /* CF /wm */ { 0, &BX_CPU_C::IRET16 },
+ /* CF /wm */ { 0, &BX_CPU_C::IRET64 },
/* D0 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
/* D1 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
/* D2 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
@@ -2502,7 +2502,7 @@
/* CC /dm */ { 0, &BX_CPU_C::INT3 },
/* CD /dm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
/* CE /dm */ { 0, &BX_CPU_C::BxError },
- /* CF /dm */ { 0, &BX_CPU_C::IRET32 },
+ /* CF /dm */ { 0, &BX_CPU_C::IRET64 },
/* D0 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
/* D1 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
/* D2 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
Index: flag_ctrl.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/flag_ctrl.cc,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- flag_ctrl.cc 22 Nov 2007 21:52:55 -0000 1.31
+++ flag_ctrl.cc 24 Nov 2007 14:22:34 -0000 1.32
@@ -31,6 +31,11 @@
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
+// Make code more tidy with a few macros.
+#if BX_SUPPORT_X86_64==0
+#define RSP ESP
+#endif
+
void BX_CPU_C::SAHF(bxInstruction_c *i)
{
@@ -214,6 +219,9 @@
BX_DEBUG(("POPFW: #GP(0) in v8086 (no VME) mode"));
exception(BX_GP_EXCEPTION, 0, 0);
}
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&flags16);
#if BX_SUPPORT_VME
if (CR4_VME_ENABLED && BX_CPU_THIS_PTR get_IOPL() < 3) {
@@ -233,6 +241,8 @@
}
#endif
changeMask |= EFlagsIFMask;
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
else {
pop_16(&flags16);
Index: init.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
retrieving revision 1.144
retrieving revision 1.145
diff -u -d -r1.144 -r1.145
--- init.cc 18 Nov 2007 21:07:40 -0000 1.144
+++ init.cc 24 Nov 2007 14:22:34 -0000 1.145
@@ -718,9 +718,9 @@
/* instruction pointer */
#if BX_CPU_LEVEL < 2
- BX_CPU_THIS_PTR prev_eip = EIP = 0x00000000;
+ BX_CPU_THIS_PTR prev_rip = EIP = 0x00000000;
#else /* from 286 up */
- BX_CPU_THIS_PTR prev_eip = RIP = 0x0000FFF0;
+ BX_CPU_THIS_PTR prev_rip = RIP = 0x0000FFF0;
#endif
/* CS (Code Segment) and descriptor cache */
Index: iret.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/iret.cc,v
retrieving revision 1.22
retrieving revision 1.23
diff -u -d -r1.22 -r1.23
--- iret.cc 17 Nov 2007 23:28:31 -0000 1.22
+++ iret.cc 24 Nov 2007 14:22:34 -0000 1.23
@@ -47,7 +47,7 @@
}
#endif
- if (BX_CPU_THIS_PTR get_NT ()) /* NT = 1: RETURN FROM NESTED TASK */
+ if (BX_CPU_THIS_PTR get_NT()) /* NT = 1: RETURN FROM NESTED TASK */
{
/* what's the deal with NT & VM ? */
Bit16u raw_link_selector;
Index: resolve64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/resolve64.cc,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- resolve64.cc 18 Nov 2007 19:46:14 -0000 1.13
+++ resolve64.cc 24 Nov 2007 14:22:34 -0000 1.14
@@ -38,13 +38,13 @@
BX_CPU_C::BxResolve32Rip(bxInstruction_c *i)
{
// RIP hasn't been bumped yet when this is called. must choose the saved value.
- RMAddr(i) = (Bit32u) (BX_CPU_THIS_PTR prev_eip + i->ilen() + (Bit32s) i->displ32u());
+ RMAddr(i) = (Bit32u) (BX_CPU_THIS_PTR prev_rip + i->ilen() + (Bit32s) i->displ32u());
}
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve64Rip(bxInstruction_c *i)
{
// RIP hasn't been bumped yet when this is called. must choose the saved value.
- RMAddr(i) = BX_CPU_THIS_PTR prev_eip + i->ilen() + (Bit32s) i->displ32u();
+ RMAddr(i) = BX_CPU_THIS_PTR prev_rip + i->ilen() + (Bit32s) i->displ32u();
}
void BX_CPP_AttrRegparmN(1)
Index: segment_ctrl_pro.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/segment_ctrl_pro.cc,v
retrieving revision 1.75
retrieving revision 1.76
diff -u -d -r1.75 -r1.76
--- segment_ctrl_pro.cc 20 Nov 2007 21:22:03 -0000 1.75
+++ segment_ctrl_pro.cc 24 Nov 2007 14:22:34 -0000 1.76
@@ -684,7 +684,7 @@
else { /* LDT */
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) {
BX_PANIC(("fetch_raw_descriptor: LDTR.valid=0"));
- debug(BX_CPU_THIS_PTR prev_eip);
+ debug(BX_CPU_THIS_PTR prev_rip);
}
if ((index*8 + 7) > BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled) {
BX_ERROR(("fetch_raw_descriptor: LDT: index (%x)%x > limit (%x)",
@@ -746,7 +746,7 @@
else { /* LDT */
if (BX_CPU_THIS_PTR ldtr.cache.valid==0) {
BX_PANIC(("fetch_raw_descriptor: LDTR.valid=0"));
- debug(BX_CPU_THIS_PTR prev_eip);
+ debug(BX_CPU_THIS_PTR prev_rip);
}
if ((index*8 + 15) > BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled) {
BX_ERROR(("fetch_raw_descriptor64: LDT: index (%x)%x > limit (%x)",
Index: smm.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/smm.cc,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -d -r1.28 -r1.29
--- smm.cc 20 Nov 2007 21:22:03 -0000 1.28
+++ smm.cc 24 Nov 2007 14:22:34 -0000 1.29
@@ -106,7 +106,7 @@
BX_INFO(("Enter to System Management Mode"));
- // debug(BX_CPU_THIS_PTR prev_eip);
+ // debug(BX_CPU_THIS_PTR prev_rip);
BX_CPU_THIS_PTR in_smm = 1;
@@ -124,7 +124,7 @@
}
BX_CPU_THIS_PTR setEFlags(0x2); // Bit1 is always set
- BX_CPU_THIS_PTR prev_eip = RIP = 0x00008000;
+ BX_CPU_THIS_PTR prev_rip = RIP = 0x00008000;
BX_CPU_THIS_PTR dr7 = 0x00000400;
// CR0 - PE, EM, TS, and PG flags set to 0; others unmodified
Index: soft_int.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/soft_int.cc,v
retrieving revision 1.34
retrieving revision 1.35
diff -u -d -r1.34 -r1.35
--- soft_int.cc 17 Nov 2007 23:28:32 -0000 1.34
+++ soft_int.cc 24 Nov 2007 14:22:34 -0000 1.35
@@ -34,6 +34,11 @@
#include "extdb.h"
#endif
+// Make code more tidy with a few macros.
+#if BX_SUPPORT_X86_64==0
+#define RSP ESP
+#endif
+
void BX_CPU_C::BOUND_GwMa(bxInstruction_c *i)
{
Bit16s bound_min, bound_max;
@@ -75,7 +80,14 @@
trap_debugger(0);
#endif
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ // interrupt is not RSP safe
interrupt(1, 1, 0, 0);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
@@ -89,7 +101,14 @@
BX_CPU_THIS_PTR show_flag |= Flag_softint;
#endif
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ // interrupt is not RSP safe
interrupt(3, 1, 0, 0);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
@@ -104,6 +123,9 @@
Bit8u vector = i->Ib();
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
if (v8086_mode()) {
#if BX_SUPPORT_VME
if (BX_CPU_THIS_PTR cr4.get_VME())
@@ -120,7 +142,7 @@
{
// redirect interrupt through virtual-mode idt
v86_redirect_interrupt(vector);
- return;
+ goto done;
}
}
#endif
@@ -139,6 +161,11 @@
#endif
interrupt(vector, 1, 0, 0);
+
+done:
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
@@ -151,7 +178,14 @@
#endif
if (get_OF()) {
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
+ // interrupt is not RSP safe
interrupt(4, 1, 0, 0);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_INT,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
EIP);
Index: stack16.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/stack16.cc,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -d -r1.26 -r1.27
--- stack16.cc 20 Nov 2007 17:15:33 -0000 1.26
+++ stack16.cc 24 Nov 2007 14:22:34 -0000 1.27
@@ -30,6 +30,10 @@
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
+// Make code more tidy with a few macros.
+#if BX_SUPPORT_X86_64==0
+#define RSP ESP
+#endif
void BX_CPU_C::PUSH_RX(bxInstruction_c *i)
{
@@ -69,37 +73,68 @@
void BX_CPU_C::POP16_DS(bxInstruction_c *i)
{
Bit16u ds;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&ds);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
}
void BX_CPU_C::POP16_ES(bxInstruction_c *i)
{
Bit16u es;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&es);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP16_FS(bxInstruction_c *i)
{
Bit16u fs;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&fs);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP16_GS(bxInstruction_c *i)
{
Bit16u gs;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&gs);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP16_SS(bxInstruction_c *i)
{
Bit16u ss;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&ss);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
// POP SS inhibits interrupts, debug exceptions and single-step
// trap exceptions until the execution boundary following the
// next instruction is reached.
@@ -120,6 +155,9 @@
{
Bit16u val16;
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_16(&val16);
// Note: there is one little weirdism here. It is possible to use
@@ -129,6 +167,8 @@
BX_CPU_CALL_METHODR (i->ResolveModrm, (i));
}
write_virtual_word(i->seg(), RMAddr(i), &val16);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP_EwR(bxInstruction_c *i)
Index: stack32.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/stack32.cc,v
retrieving revision 1.40
retrieving revision 1.41
diff -u -d -r1.40 -r1.41
--- stack32.cc 22 Nov 2007 17:33:06 -0000 1.40
+++ stack32.cc 24 Nov 2007 14:22:34 -0000 1.41
@@ -30,10 +30,18 @@
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
+// Make code more tidy with a few macros.
+#if BX_SUPPORT_X86_64==0
+#define RSP ESP
+#endif
+
void BX_CPU_C::POP_EdM(bxInstruction_c *i)
{
Bit32u val32;
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_32(&val32);
// Note: there is one little weirdism here. It is possible to use
@@ -44,6 +52,8 @@
BX_CPU_CALL_METHODR (i->ResolveModrm, (i));
}
write_virtual_dword(i->seg(), RMAddr(i), &val32);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP_EdR(bxInstruction_c *i)
@@ -79,6 +89,13 @@
decrementESPForPush(4, &eSP);
write_virtual_word(BX_SEG_REG_SS, eSP,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
+
+ if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
+ ESP = eSP;
+ }
+ else {
+ SP = (Bit16u) eSP;
+ }
}
void BX_CPU_C::PUSH32_ES(bxInstruction_c *i)
@@ -87,6 +104,13 @@
decrementESPForPush(4, &eSP);
write_virtual_word(BX_SEG_REG_SS, eSP,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
+
+ if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
+ ESP = eSP;
+ }
+ else {
+ SP = (Bit16u) eSP;
+ }
}
void BX_CPU_C::PUSH32_FS(bxInstruction_c *i)
@@ -95,6 +119,13 @@
decrementESPForPush(4, &eSP);
write_virtual_word(BX_SEG_REG_SS, eSP,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
+
+ if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
+ ESP = eSP;
+ }
+ else {
+ SP = (Bit16u) eSP;
+ }
}
void BX_CPU_C::PUSH32_GS(bxInstruction_c *i)
@@ -103,6 +134,13 @@
decrementESPForPush(4, &eSP);
write_virtual_word(BX_SEG_REG_SS, eSP,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
+
+ if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
+ ESP = eSP;
+ }
+ else {
+ SP = (Bit16u) eSP;
+ }
}
void BX_CPU_C::PUSH32_SS(bxInstruction_c *i)
@@ -111,42 +149,79 @@
decrementESPForPush(4, &eSP);
write_virtual_word(BX_SEG_REG_SS, eSP,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
+
+ if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
+ ESP = eSP;
+ }
+ else {
+ SP = (Bit16u) eSP;
+ }
}
void BX_CPU_C::POP32_DS(bxInstruction_c *i)
{
Bit32u ds;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_32(&ds);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], (Bit16u) ds);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP32_ES(bxInstruction_c *i)
{
Bit32u es;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_32(&es);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], (Bit16u) es);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP32_FS(bxInstruction_c *i)
{
Bit32u fs;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_32(&fs);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], (Bit16u) fs);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP32_GS(bxInstruction_c *i)
{
Bit32u gs;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_32(&gs);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], (Bit16u) gs);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP32_SS(bxInstruction_c *i)
{
Bit32u ss;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_32(&ss);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], (Bit16u) ss);
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
// POP SS inhibits interrupts, debug exceptions and single-step
// trap exceptions until the execution boundary following the
// next instruction is reached.
@@ -254,6 +329,9 @@
Bit8u level = i->Ib2();
level &= 0x1F;
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
Bit32u ebp; // Use temp copy in case of exception.
push_16(BP);
@@ -286,6 +364,8 @@
push_16((Bit16u)frame_ptr32);
}
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
if (ss32) {
EBP = frame_ptr32;
ESP -= imm16;
@@ -304,6 +384,9 @@
Bit8u level = i->Ib2();
level &= 0x1F;
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
Bit32u ebp; // Use temp copy in case of exception.
push_32(EBP);
@@ -336,6 +419,8 @@
push_32(frame_ptr32);
}
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+
if (ss32) {
EBP = frame_ptr32;
ESP -= imm16;
@@ -372,13 +457,16 @@
}
}
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
// delete frame
#if BX_CPU_LEVEL >= 3
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
ESP = EBP;
else
#endif
- SP = BP;
+ SP = BP;
// restore frame pointer
#if BX_CPU_LEVEL >= 3
@@ -394,5 +482,7 @@
pop_16(&temp16);
BP = temp16;
}
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
#endif
Index: stack64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/stack64.cc,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -d -r1.28 -r1.29
--- stack64.cc 22 Nov 2007 21:52:55 -0000 1.28
+++ stack64.cc 24 Nov 2007 14:22:34 -0000 1.29
@@ -36,6 +36,9 @@
{
Bit64u val64;
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_64(&val64);
// Note: there is one little weirdism here. It is possible to use
@@ -46,6 +49,8 @@
BX_CPU_CALL_METHODR (i->ResolveModrm, (i));
}
write_virtual_qword(i->seg(), RMAddr(i), &val64);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP_EqR(bxInstruction_c *i)
@@ -57,7 +62,7 @@
void BX_CPU_C::PUSH_RRX(bxInstruction_c *i)
{
- push_64(BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].rrx);
+ push_64(BX_READ_64BIT_REG(i->opcodeReg()));
}
void BX_CPU_C::POP_RRX(bxInstruction_c *i)
@@ -80,15 +85,27 @@
void BX_CPU_C::POP64_FS(bxInstruction_c *i)
{
Bit64u fs;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_64(&fs);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], (Bit16u) fs);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::POP64_GS(bxInstruction_c *i)
{
Bit64u gs;
+
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
pop_64(&gs);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], (Bit16u) gs);
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
void BX_CPU_C::PUSH64_Id(bxInstruction_c *i)
@@ -118,6 +135,9 @@
level &= 0x1F;
Bit64u bytes_to_push = 8 + level*8 + i->Iw();
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
push_64(RBP);
Bit64u frame_ptr64 = RSP;
@@ -138,13 +158,17 @@
write_virtual_qword(BX_SEG_REG_SS, RSP, &frame_ptr64);
} /* if (level > 0) ... */
- RBP = frame_ptr64;
+ BX_CPU_THIS_PTR speculative_rsp = 0;
+ RBP = frame_ptr64;
RSP -= i->Iw();
}
void BX_CPU_C::LEAVE64(bxInstruction_c *i)
{
+ BX_CPU_THIS_PTR speculative_rsp = 1;
+ BX_CPU_THIS_PTR prev_rsp = RSP;
+
// delete frame
RSP = RBP;
@@ -152,6 +176,8 @@
Bit64u temp64;
pop_64(&temp64);
RBP = temp64;
+
+ BX_CPU_THIS_PTR speculative_rsp = 0;
}
#endif /* if BX_SUPPORT_X86_64 */
Index: stack_pro.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/stack_pro.cc,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- stack_pro.cc 17 Nov 2007 23:28:33 -0000 1.31
+++ stack_pro.cc 24 Nov 2007 14:22:34 -0000 1.32
@@ -353,11 +353,9 @@
// And finally, decrement eSP and return the new eSP value.
eSP -= nBytes;
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
- ESP = eSP;
*eSP_ptr = eSP;
}
else {
- SP = (Bit16u) eSP;
*eSP_ptr = SP;
}
}
Index: tasking.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/tasking.cc,v
retrieving revision 1.41
retrieving revision 1.42
diff -u -d -r1.41 -r1.42
--- tasking.cc 20 Nov 2007 21:22:03 -0000 1.41
+++ tasking.cc 24 Nov 2007 14:22:34 -0000 1.42
@@ -429,7 +429,7 @@
}
}
- BX_CPU_THIS_PTR prev_eip = EIP = newEIP;
+ BX_CPU_THIS_PTR prev_rip = EIP = newEIP;
EAX = newEAX;
ECX = newECX;
-------------------------------------------------------------------------
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