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List:       bochs-cvs
Subject:    [Bochs-cvs] CVS: bochs/disasm dis_tables.inc, 1.8, 1.9 resolve.cc,
From:       Stanislav Shwartsman <sshwarts () users ! sourceforge ! net>
Date:       2006-06-26 21:06:28
Message-ID: E1FuyHs-0007Qq-O9 () sc8-pr-cvs3 ! sourceforge ! net
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Update of /cvsroot/bochs/bochs/disasm
In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv28110

Modified Files:
	dis_tables.inc resolve.cc 
Log Message:
Fixed DR registers disasm 


Index: dis_tables.inc
===================================================================
RCS file: /cvsroot/bochs/bochs/disasm/dis_tables.inc,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- dis_tables.inc	7 May 2006 19:12:55 -0000	1.8
+++ dis_tables.inc	26 Jun 2006 21:06:26 -0000	1.9
@@ -3819,9 +3819,9 @@
   /* 0F 1E */ { 0, &Ia_Invalid    },
   /* 0F 1F */ { 0, &Ia_multibyte_nop },
   /* 0F 20 */ { 0, &Ia_movq_Rq_Cq },
-  /* 0F 21 */ { 0, &Ia_movl_Rd_Dd },
+  /* 0F 21 */ { 0, &Ia_movq_Rq_Dq },
   /* 0F 22 */ { 0, &Ia_movq_Cq_Rq },
-  /* 0F 23 */ { 0, &Ia_movl_Dd_Rd },
+  /* 0F 23 */ { 0, &Ia_movq_Dq_Rq },
   /* 0F 24 */ { 0, &Ia_Invalid    },
   /* 0F 25 */ { 0, &Ia_Invalid    },
   /* 0F 26 */ { 0, &Ia_Invalid    },
@@ -4337,9 +4337,9 @@
   /* 0F 1E */ { 0, &Ia_Invalid    },
   /* 0F 1F */ { 0, &Ia_multibyte_nop },
   /* 0F 20 */ { 0, &Ia_movq_Rq_Cq },
-  /* 0F 21 */ { 0, &Ia_movl_Rd_Dd },
+  /* 0F 21 */ { 0, &Ia_movq_Rq_Dq },
   /* 0F 22 */ { 0, &Ia_movq_Cq_Rq },
-  /* 0F 23 */ { 0, &Ia_movl_Dd_Rd },
+  /* 0F 23 */ { 0, &Ia_movq_Dq_Rq },
   /* 0F 24 */ { 0, &Ia_Invalid    },
   /* 0F 25 */ { 0, &Ia_Invalid    },
   /* 0F 26 */ { 0, &Ia_Invalid    },

Index: resolve.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/disasm/resolve.cc,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- resolve.cc	27 Apr 2006 15:11:45 -0000	1.11
+++ resolve.cc	26 Jun 2006 21:06:26 -0000	1.12
@@ -9,6 +9,8 @@
 {
   insn->modrm = fetch_byte();
   BX_DECODE_MODRM(insn->modrm, insn->mod, insn->nnn, insn->rm);
+  // MOVs with CRx and DRx always use register ops and ignore the mod field.
+  if ((insn->b1 & ~3) == 0x120) insn->mod = 3;
   insn->nnn |= insn->rex_r;
 
   if (insn->mod == 3) {


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