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List: bochs-cvs
Subject: [Bochs-cvs] CVS: bochs/cpu bit.cc,1.23,1.24 cpu.h,1.225,1.226 fetchdecode.cc,1.80,1.81 fetchdecode64
From: Stanislav Shwartsman <sshwarts () users ! sourceforge ! net>
Date: 2005-07-25 4:18:23
Message-ID: E1DwuQ3-00036z-2N () sc8-pr-cvs1 ! sourceforge ! net
[Download RAW message or body]
Update of /cvsroot/bochs/bochs/cpu
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv11839/cpu
Modified Files:
bit.cc cpu.h fetchdecode.cc fetchdecode64.cc lazy_flags.h
Log Message:
Split last bit.cc methods according to os16/32/64
Index: bit.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/bit.cc,v
retrieving revision 1.23
retrieving revision 1.24
diff -u -d -r1.23 -r1.24
--- bit.cc 20 May 2005 20:06:50 -0000 1.23
+++ bit.cc 25 Jul 2005 04:18:10 -0000 1.24
@@ -1209,328 +1209,324 @@
}
#endif
-void BX_CPU_C::BT_EvIb(bxInstruction_c *i)
+void BX_CPU_C::BT_EwIb(bxInstruction_c *i)
{
-#if BX_SUPPORT_X86_64
- if (i->os64L()) { /* 64 bit operand size mode */
- /* for 64 bit operand size mode */
- Bit64u op1_64;
-
- Bit8u op2_8 = i->Ib() & 0x3f;
+ Bit16u op1_16;
- /* op1_64 is a register or memory reference */
- if (i->modC0()) {
- op1_64 = BX_READ_64BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
- }
+ Bit8u op2_8 = i->Ib() & 0xf;
- set_CF((op1_64 >> op2_8) & 0x01);
+ /* op1_16 is a register or memory reference */
+ if (i->modC0()) {
+ op1_16 = BX_READ_16BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
- else
-#endif // #if BX_SUPPORT_X86_64
- if (i->os32L()) { /* 32 bit operand size mode */
- /* for 32 bit operand size mode */
- Bit32u op1_32;
- Bit8u op2_8 = i->Ib() & 0x1f;
+ set_CF((op1_16 >> op2_8) & 0x01);
+}
- /* op1_32 is a register or memory reference */
- if (i->modC0()) {
- op1_32 = BX_READ_32BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
- }
+void BX_CPU_C::BT_EdIb(bxInstruction_c *i)
+{
+ Bit32u op1_32;
- set_CF((op1_32 >> op2_8) & 0x01);
+ Bit8u op2_8 = i->Ib() & 0x1f;
+
+ /* op1_32 is a register or memory reference */
+ if (i->modC0()) {
+ op1_32 = BX_READ_32BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
- else { /* 16 bit operand size mode */
- Bit16u op1_16;
- Bit8u op2_8 = i->Ib() & 0xf;
+ set_CF((op1_32 >> op2_8) & 0x01);
+}
- /* op1_16 is a register or memory reference */
- if (i->modC0()) {
- op1_16 = BX_READ_16BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_virtual_word(i->seg(), RMAddr(i), &op1_16);
- }
+#if BX_SUPPORT_X86_64
+void BX_CPU_C::BT_EqIb(bxInstruction_c *i)
+{
+ Bit64u op1_64;
- set_CF((op1_16 >> op2_8) & 0x01);
- }
+ Bit8u op2_8 = i->Ib() & 0x3f;
+
+ /* op1_64 is a register or memory reference */
+ if (i->modC0()) {
+ op1_64 = BX_READ_64BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
+ }
+
+ set_CF((op1_64 >> op2_8) & 0x01);
}
+#endif
-void BX_CPU_C::BTS_EvIb(bxInstruction_c *i)
+void BX_CPU_C::BTS_EwIb(bxInstruction_c *i)
{
-#if BX_SUPPORT_X86_64
- if (i->os64L()) { /* 64 bit operand size mode */
- /* for 64 bit operand size mode */
- Bit64u op1_64;
-
- Bit8u op2_8 = i->Ib() & 0x3f;
+ Bit16u op1_16;
- /* op1_64 is a register or memory reference */
- if (i->modC0()) {
- op1_64 = BX_READ_64BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
- }
+ Bit8u op2_8 = i->Ib() & 0xf;
- bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
- op1_64 |= (((Bit64u) 1) << op2_8);
+ /* op1_16 is a register or memory reference */
+ if (i->modC0()) {
+ op1_16 = BX_READ_16BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
+ }
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_64BIT_REG(i->rm(), op1_64);
- }
- else {
- Write_RMW_virtual_qword(op1_64);
- }
+ bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
+ op1_16 |= (((Bit16u) 1) << op2_8);
- set_CF(temp_CF);
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_16BIT_REG(i->rm(), op1_16);
+ }
+ else {
+ Write_RMW_virtual_word(op1_16);
}
- else
-#endif // #if BX_SUPPORT_X86_64
- if (i->os32L()) { /* 32 bit operand size mode */
- /* for 32 bit operand size mode */
- Bit32u op1_32;
- Bit8u op2_8 = i->Ib() & 0x1f;
+ set_CF(temp_CF);
+}
- /* op1_32 is a register or memory reference */
- if (i->modC0()) {
- op1_32 = BX_READ_32BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
- }
+void BX_CPU_C::BTS_EdIb(bxInstruction_c *i)
+{
+ Bit32u op1_32;
- bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
- op1_32 |= (((Bit32u) 1) << op2_8);
+ Bit8u op2_8 = i->Ib() & 0x1f;
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
- }
- else {
- Write_RMW_virtual_dword(op1_32);
- }
+ /* op1_32 is a register or memory reference */
+ if (i->modC0()) {
+ op1_32 = BX_READ_32BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
+ }
- set_CF(temp_CF);
+ bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
+ op1_32 |= (((Bit32u) 1) << op2_8);
+
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
+ }
+ else {
+ Write_RMW_virtual_dword(op1_32);
}
- else { /* 16 bit operand size mode */
- Bit16u op1_16;
- Bit8u op2_8 = i->Ib() & 0xf;
+ set_CF(temp_CF);
+}
- /* op1_16 is a register or memory reference */
- if (i->modC0()) {
- op1_16 = BX_READ_16BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
- }
+#if BX_SUPPORT_X86_64
+void BX_CPU_C::BTS_EqIb(bxInstruction_c *i)
+{
+ Bit64u op1_64;
- bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
- op1_16 |= (((Bit16u) 1) << op2_8);
+ Bit8u op2_8 = i->Ib() & 0x3f;
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_16BIT_REG(i->rm(), op1_16);
- }
- else {
- Write_RMW_virtual_word(op1_16);
- }
+ /* op1_64 is a register or memory reference */
+ if (i->modC0()) {
+ op1_64 = BX_READ_64BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
+ }
- set_CF(temp_CF);
+ bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
+ op1_64 |= (((Bit64u) 1) << op2_8);
+
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
+ else {
+ Write_RMW_virtual_qword(op1_64);
+ }
+
+ set_CF(temp_CF);
}
+#endif
-void BX_CPU_C::BTC_EvIb(bxInstruction_c *i)
+void BX_CPU_C::BTC_EwIb(bxInstruction_c *i)
{
-#if BX_SUPPORT_X86_64
- if (i->os64L()) { /* 64 bit operand size mode */
- /* for 64 bit operand size mode */
- Bit64u op1_64;
+ Bit16u op1_16;
- Bit8u op2_8 = i->Ib() & 0x3f;
+ Bit8u op2_8 = i->Ib() & 0xf;
- /* op1_64 is a register or memory reference */
- if (i->modC0()) {
- op1_64 = BX_READ_64BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
- }
+ /* op1_16 is a register or memory reference */
+ if (i->modC0()) {
+ op1_16 = BX_READ_16BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
+ }
- bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
- op1_64 ^= (((Bit64u) 1) << op2_8); /* toggle bit */
- set_CF(temp_CF);
+ bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
+ op1_16 ^= (((Bit16u) 1) << op2_8); /* toggle bit */
+ set_CF(temp_CF);
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_64BIT_REG(i->rm(), op1_64);
- }
- else {
- Write_RMW_virtual_qword(op1_64);
- }
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
- else
-#endif // #if BX_SUPPORT_X86_64
- if (i->os32L()) { /* 32 bit operand size mode */
- /* for 32 bit operand size mode */
- Bit32u op1_32;
+ else {
+ Write_RMW_virtual_word(op1_16);
+ }
+}
- Bit8u op2_8 = i->Ib() & 0x1f;
+void BX_CPU_C::BTC_EdIb(bxInstruction_c *i)
+{
+ Bit32u op1_32;
- /* op1_32 is a register or memory reference */
- if (i->modC0()) {
- op1_32 = BX_READ_32BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
- }
+ Bit8u op2_8 = i->Ib() & 0x1f;
- bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
- op1_32 ^= (((Bit32u) 1) << op2_8); /* toggle bit */
- set_CF(temp_CF);
+ /* op1_32 is a register or memory reference */
+ if (i->modC0()) {
+ op1_32 = BX_READ_32BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
+ }
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
- }
- else {
- Write_RMW_virtual_dword(op1_32);
- }
+ bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
+ op1_32 ^= (((Bit32u) 1) << op2_8); /* toggle bit */
+ set_CF(temp_CF);
+
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
- else { /* 16 bit operand size mode */
- Bit16u op1_16;
+ else {
+ Write_RMW_virtual_dword(op1_32);
+ }
+}
- Bit8u op2_8 = i->Ib() & 0xf;
+#if BX_SUPPORT_X86_64
+void BX_CPU_C::BTC_EqIb(bxInstruction_c *i)
+{
+ Bit64u op1_64;
- /* op1_16 is a register or memory reference */
- if (i->modC0()) {
- op1_16 = BX_READ_16BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
- }
+ Bit8u op2_8 = i->Ib() & 0x3f;
- bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
- op1_16 ^= (((Bit16u) 1) << op2_8); /* toggle bit */
- set_CF(temp_CF);
+ /* op1_64 is a register or memory reference */
+ if (i->modC0()) {
+ op1_64 = BX_READ_64BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
+ }
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_16BIT_REG(i->rm(), op1_16);
- }
- else {
- Write_RMW_virtual_word(op1_16);
- }
+ bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
+ op1_64 ^= (((Bit64u) 1) << op2_8); /* toggle bit */
+ set_CF(temp_CF);
+
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_64BIT_REG(i->rm(), op1_64);
+ }
+ else {
+ Write_RMW_virtual_qword(op1_64);
}
}
+#endif
-void BX_CPU_C::BTR_EvIb(bxInstruction_c *i)
+void BX_CPU_C::BTR_EwIb(bxInstruction_c *i)
{
-#if BX_SUPPORT_X86_64
- if (i->os64L()) { /* 64 bit operand size mode */
- /* for 64 bit operand size mode */
- Bit64u op1_64;
-
- Bit8u op2_8 = i->Ib() & 0x3f;
+ Bit16u op1_16;
- /* op1_64 is a register or memory reference */
- if (i->modC0()) {
- op1_64 = BX_READ_64BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
- }
+ Bit8u op2_8 = i->Ib() & 0xf;
- bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
- op1_64 &= ~(((Bit64u) 1) << op2_8);
+ /* op1_16 is a register or memory reference */
+ if (i->modC0()) {
+ op1_16 = BX_READ_16BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
+ }
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_64BIT_REG(i->rm(), op1_64);
- }
- else {
- Write_RMW_virtual_qword(op1_64);
- }
+ bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
+ op1_16 &= ~(((Bit16u) 1) << op2_8);
- set_CF(temp_CF);
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_16BIT_REG(i->rm(), op1_16);
+ }
+ else {
+ Write_RMW_virtual_word(op1_16);
}
- else
-#endif // #if BX_SUPPORT_X86_64
- if (i->os32L()) { /* 32 bit operand size mode */
- /* for 32 bit operand size mode */
- Bit32u op1_32;
- Bit8u op2_8 = i->Ib() & 0x1f;
+ set_CF(temp_CF);
+}
- /* op1_32 is a register or memory reference */
- if (i->modC0()) {
- op1_32 = BX_READ_32BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
- }
+void BX_CPU_C::BTR_EdIb(bxInstruction_c *i)
+{
+ Bit32u op1_32;
- bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
- op1_32 &= ~(((Bit32u) 1) << op2_8);
+ Bit8u op2_8 = i->Ib() & 0x1f;
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
- }
- else {
- Write_RMW_virtual_dword(op1_32);
- }
+ /* op1_32 is a register or memory reference */
+ if (i->modC0()) {
+ op1_32 = BX_READ_32BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
+ }
- set_CF(temp_CF);
+ bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
+ op1_32 &= ~(((Bit32u) 1) << op2_8);
+
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
+ }
+ else {
+ Write_RMW_virtual_dword(op1_32);
}
- else { /* 16 bit operand size mode */
- Bit16u op1_16;
- Bit8u op2_8 = i->Ib() & 0xf;
+ set_CF(temp_CF);
+}
- /* op1_16 is a register or memory reference */
- if (i->modC0()) {
- op1_16 = BX_READ_16BIT_REG(i->rm());
- }
- else {
- /* pointer, segment address pair */
- read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
- }
+#if BX_SUPPORT_X86_64
+void BX_CPU_C::BTR_EqIb(bxInstruction_c *i)
+{
+ Bit64u op1_64;
- bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
- op1_16 &= ~(((Bit16u) 1) << op2_8);
+ Bit8u op2_8 = i->Ib() & 0x3f;
- /* now write diff back to destination */
- if (i->modC0()) {
- BX_WRITE_16BIT_REG(i->rm(), op1_16);
- }
- else {
- Write_RMW_virtual_word(op1_16);
- }
+ /* op1_64 is a register or memory reference */
+ if (i->modC0()) {
+ op1_64 = BX_READ_64BIT_REG(i->rm());
+ }
+ else {
+ /* pointer, segment address pair */
+ read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
+ }
- set_CF(temp_CF);
+ bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
+ op1_64 &= ~(((Bit64u) 1) << op2_8);
+
+ /* now write diff back to destination */
+ if (i->modC0()) {
+ BX_WRITE_64BIT_REG(i->rm(), op1_64);
+ }
+ else {
+ Write_RMW_virtual_qword(op1_64);
}
+
+ set_CF(temp_CF);
}
+#endif
#endif /* BX_CPU_LEVEL >= 3 */
Index: cpu.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
retrieving revision 1.225
retrieving revision 1.226
diff -u -d -r1.225 -r1.226
--- cpu.h 21 Jul 2005 01:59:03 -0000 1.225
+++ cpu.h 25 Jul 2005 04:18:10 -0000 1.226
@@ -1564,12 +1564,21 @@
BX_SMF void BT_EwGw(bxInstruction_c *);
BX_SMF void BT_EdGd(bxInstruction_c *);
+ BX_SMF void BT_EwIb(bxInstruction_c *);
+ BX_SMF void BT_EdIb(bxInstruction_c *);
+
BX_SMF void BTS_EwGw(bxInstruction_c *);
BX_SMF void BTS_EdGd(bxInstruction_c *);
+ BX_SMF void BTS_EwIb(bxInstruction_c *);
+ BX_SMF void BTS_EdIb(bxInstruction_c *);
BX_SMF void BTR_EwGw(bxInstruction_c *);
BX_SMF void BTR_EdGd(bxInstruction_c *);
+ BX_SMF void BTR_EwIb(bxInstruction_c *);
+ BX_SMF void BTR_EdIb(bxInstruction_c *);
BX_SMF void BTC_EwGw(bxInstruction_c *);
BX_SMF void BTC_EdGd(bxInstruction_c *);
+ BX_SMF void BTC_EwIb(bxInstruction_c *);
+ BX_SMF void BTC_EdIb(bxInstruction_c *);
BX_SMF void LES_GvMp(bxInstruction_c *);
BX_SMF void LDS_GvMp(bxInstruction_c *);
@@ -1692,11 +1701,6 @@
BX_SMF void SMSW_Ew(bxInstruction_c *);
BX_SMF void LMSW_Ew(bxInstruction_c *);
- BX_SMF void BT_EvIb(bxInstruction_c *);
- BX_SMF void BTS_EvIb(bxInstruction_c *);
- BX_SMF void BTR_EvIb(bxInstruction_c *);
- BX_SMF void BTC_EvIb(bxInstruction_c *);
-
#if BX_SUPPORT_FPU == 0 // if FPU is disabled
BX_SMF void FPU_ESC(bxInstruction_c *);
#endif
@@ -2359,9 +2363,14 @@
BX_SMF void BSR_GqEq(bxInstruction_c *);
BX_SMF void BT_EqGq(bxInstruction_c *);
+ BX_SMF void BT_EqIb(bxInstruction_c *);
+
BX_SMF void BTS_EqGq(bxInstruction_c *);
+ BX_SMF void BTS_EqIb(bxInstruction_c *);
BX_SMF void BTR_EqGq(bxInstruction_c *);
+ BX_SMF void BTR_EqIb(bxInstruction_c *);
BX_SMF void BTC_EqGq(bxInstruction_c *);
+ BX_SMF void BTC_EqIb(bxInstruction_c *);
BX_SMF void BSWAP_RAX(bxInstruction_c *);
BX_SMF void BSWAP_RCX(bxInstruction_c *);
Index: fetchdecode.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode.cc,v
retrieving revision 1.80
retrieving revision 1.81
diff -u -d -r1.80 -r1.81
--- fetchdecode.cc 21 Jun 2005 17:01:18 -0000 1.80
+++ fetchdecode.cc 25 Jul 2005 04:18:10 -0000 1.81
@@ -305,16 +305,26 @@
/* 7 */ { 0, &BX_CPU_C::INVLPG }
};
+static BxOpcodeInfo_t BxOpcodeInfoG8EwIb[8] = {
+ /* 0 */ { 0, &BX_CPU_C::BxError },
+ /* 1 */ { 0, &BX_CPU_C::BxError },
+ /* 2 */ { 0, &BX_CPU_C::BxError },
+ /* 3 */ { 0, &BX_CPU_C::BxError },
+ /* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EwIb },
+ /* 5 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTS_EwIb },
+ /* 6 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTR_EwIb },
+ /* 7 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTC_EwIb }
+ };
-static BxOpcodeInfo_t BxOpcodeInfoG8EvIb[8] = {
+static BxOpcodeInfo_t BxOpcodeInfoG8EdIb[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
- /* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EvIb },
- /* 5 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTS_EvIb },
- /* 6 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTR_EvIb },
- /* 7 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTC_EvIb }
+ /* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EdIb },
+ /* 5 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTS_EdIb },
+ /* 6 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTR_EdIb },
+ /* 7 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTC_EdIb }
};
static BxOpcodeInfo_t BxOpcodeInfoG9[8] = {
@@ -862,7 +872,7 @@
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GwEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
- /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EvIb },
+ /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EwIb },
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EwGw },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GwEw },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GwEw },
@@ -1405,7 +1415,7 @@
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GdEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
- /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EvIb },
+ /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfoG8EdIb },
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EdGd },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GdEd },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GdEd },
Index: fetchdecode64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode64.cc,v
retrieving revision 1.78
retrieving revision 1.79
diff -u -d -r1.78 -r1.79
--- fetchdecode64.cc 21 Jun 2005 17:01:19 -0000 1.78
+++ fetchdecode64.cc 25 Jul 2005 04:18:11 -0000 1.79
@@ -412,16 +412,37 @@
/* 7 */ { 0, &BX_CPU_C::INVLPG }
};
+static BxOpcodeInfo_t BxOpcodeInfo64G8EwIb[8] = {
+ /* 0 */ { 0, &BX_CPU_C::BxError },
+ /* 1 */ { 0, &BX_CPU_C::BxError },
+ /* 2 */ { 0, &BX_CPU_C::BxError },
+ /* 3 */ { 0, &BX_CPU_C::BxError },
+ /* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EwIb },
+ /* 5 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTS_EwIb },
+ /* 6 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTR_EwIb },
+ /* 7 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTC_EwIb }
+ };
-static BxOpcodeInfo_t BxOpcodeInfo64G8EvIb[8] = {
+static BxOpcodeInfo_t BxOpcodeInfo64G8EdIb[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
- /* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EvIb },
- /* 5 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTS_EvIb },
- /* 6 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTR_EvIb },
- /* 7 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTC_EvIb }
+ /* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EdIb },
+ /* 5 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTS_EdIb },
+ /* 6 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTR_EdIb },
+ /* 7 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTC_EdIb }
+ };
+
+static BxOpcodeInfo_t BxOpcodeInfo64G8EqIb[8] = {
+ /* 0 */ { 0, &BX_CPU_C::BxError },
+ /* 1 */ { 0, &BX_CPU_C::BxError },
+ /* 2 */ { 0, &BX_CPU_C::BxError },
+ /* 3 */ { 0, &BX_CPU_C::BxError },
+ /* 4 */ { BxImmediate_Ib, &BX_CPU_C::BT_EqIb },
+ /* 5 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTS_EqIb },
+ /* 6 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTR_EqIb },
+ /* 7 */ { BxImmediate_Ib | BxLockable, &BX_CPU_C::BTC_EqIb }
};
static BxOpcodeInfo_t BxOpcodeInfo64G9[8] = {
@@ -956,7 +977,7 @@
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GwEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
- /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
+ /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EwIb },
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EwGw },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GwEw },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GwEw },
@@ -1478,7 +1499,7 @@
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GdEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
- /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
+ /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EdIb },
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EdGd },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GdEd },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GdEd },
@@ -2000,7 +2021,7 @@
/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GqEw },
/* 0F B8 */ { 0, &BX_CPU_C::BxError },
/* 0F B9 */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
- /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EvIb },
+ /* 0F BA */ { BxAnother | BxGroup8, NULL, BxOpcodeInfo64G8EqIb },
/* 0F BB */ { BxAnother | BxLockable, &BX_CPU_C::BTC_EqGq },
/* 0F BC */ { BxAnother, &BX_CPU_C::BSF_GqEq },
/* 0F BD */ { BxAnother, &BX_CPU_C::BSR_GqEq },
Index: lazy_flags.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/lazy_flags.h,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- lazy_flags.h 24 Jul 2005 08:35:15 -0000 1.21
+++ lazy_flags.h 25 Jul 2005 04:18:20 -0000 1.22
@@ -38,10 +38,10 @@
#define BX_INSTR_ADC32 7
#define BX_INSTR_ADC64 8
-#define BX_INSTR_ADD_ADC8(cf) (1 + (cf<<2))
-#define BX_INSTR_ADD_ADC16(cf) (2 + (cf<<2))
-#define BX_INSTR_ADD_ADC32(cf) (3 + (cf<<2))
-#define BX_INSTR_ADD_ADC64(cf) (4 + (cf<<2))
+#define BX_INSTR_ADD_ADC8(cf) (1 + ((cf)<<2))
+#define BX_INSTR_ADD_ADC16(cf) (2 + ((cf)<<2))
+#define BX_INSTR_ADD_ADC32(cf) (3 + ((cf)<<2))
+#define BX_INSTR_ADD_ADC64(cf) (4 + ((cf)<<2))
#define BX_INSTR_SUB8 9
#define BX_INSTR_SUB16 10
@@ -54,10 +54,10 @@
#define BX_INSTR_SBB32 15
#define BX_INSTR_SBB64 16
-#define BX_INSTR_SUB_SBB8(cf) (9 + (cf<<2))
-#define BX_INSTR_SUB_SBB16(cf) (10 + (cf<<2))
-#define BX_INSTR_SUB_SBB32(cf) (11 + (cf<<2))
-#define BX_INSTR_SUB_SBB64(cf) (12 + (cf<<2))
+#define BX_INSTR_SUB_SBB8(cf) (9 + ((cf)<<2))
+#define BX_INSTR_SUB_SBB16(cf) (10 + ((cf)<<2))
+#define BX_INSTR_SUB_SBB32(cf) (11 + ((cf)<<2))
+#define BX_INSTR_SUB_SBB64(cf) (12 + ((cf)<<2))
#define BX_INSTR_INC8 17
#define BX_INSTR_INC16 18
-------------------------------------------------------
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