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List: bochs-cvs
Subject: [Bochs-cvs] CVS: bochs/cpu arith32.cc,1.44,1.45 arith64.cc,1.25,1.26 cpu.h,1.219,1.220 cpuid.cc,1.25
From: Stanislav Shwartsman <sshwarts () users ! sourceforge ! net>
Date: 2005-05-19 20:25:20
Message-ID: E1DYra4-0002do-0f () sc8-pr-cvs1 ! sourceforge ! net
[Download RAW message or body]
Update of /cvsroot/bochs/bochs/cpu
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv9923/cpu
Modified Files:
arith32.cc arith64.cc cpu.h cpuid.cc fetchdecode64.cc
Log Message:
CMPXCHG16B instruction implemented
Index: arith32.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/arith32.cc,v
retrieving revision 1.44
retrieving revision 1.45
diff -u -d -r1.44 -r1.45
--- arith32.cc 2 Apr 2005 18:49:44 -0000 1.44
+++ arith32.cc 19 May 2005 20:25:14 -0000 1.45
@@ -38,8 +38,7 @@
#endif
- void
-BX_CPU_C::INC_ERX(bxInstruction_c *i)
+void BX_CPU_C::INC_ERX(bxInstruction_c *i)
{
unsigned opcodeReg = i->opcodeReg();
@@ -55,8 +54,7 @@
BX_CLEAR_64BIT_HIGH(opcodeReg);
}
- void
-BX_CPU_C::DEC_ERX(bxInstruction_c *i)
+void BX_CPU_C::DEC_ERX(bxInstruction_c *i)
{
unsigned opcodeReg = i->opcodeReg();
@@ -72,8 +70,7 @@
BX_CLEAR_64BIT_HIGH(opcodeReg);
}
- void
-BX_CPU_C::ADD_EdGd(bxInstruction_c *i)
+void BX_CPU_C::ADD_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, sum_32;
@@ -83,18 +80,17 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
sum_32 = op1_32 + op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
sum_32 = op1_32 + op2_32;
Write_RMW_virtual_dword(sum_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
}
- void
-BX_CPU_C::ADD_GdEEd(bxInstruction_c *i)
+void BX_CPU_C::ADD_GdEEd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
unsigned nnn = i->nnn();
@@ -115,8 +111,7 @@
BX_WRITE_32BIT_REGZ(nnn, sum_32);
}
- void
-BX_CPU_C::ADD_GdEGd(bxInstruction_c *i)
+void BX_CPU_C::ADD_GdEGd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
unsigned nnn = i->nnn();
@@ -136,8 +131,7 @@
BX_WRITE_32BIT_REGZ(nnn, sum_32);
}
- void
-BX_CPU_C::ADD_EAXId(bxInstruction_c *i)
+void BX_CPU_C::ADD_EAXId(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
@@ -150,8 +144,7 @@
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
}
- void
-BX_CPU_C::ADC_EdGd(bxInstruction_c *i)
+void BX_CPU_C::ADC_EdGd(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -163,19 +156,18 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
sum_32 = op1_32 + op2_32 + temp_CF;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
sum_32 = op1_32 + op2_32 + temp_CF;
Write_RMW_virtual_dword(sum_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32,
(temp_CF) ? BX_INSTR_ADC32 : BX_INSTR_ADD32);
}
- void
-BX_CPU_C::ADC_GdEd(bxInstruction_c *i)
+void BX_CPU_C::ADC_GdEd(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -185,10 +177,10 @@
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
- }
+ }
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
- }
+ }
sum_32 = op1_32 + op2_32 + temp_CF;
@@ -198,8 +190,7 @@
(temp_CF) ? BX_INSTR_ADC32 : BX_INSTR_ADD32);
}
- void
-BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
+void BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -215,8 +206,7 @@
(temp_CF) ? BX_INSTR_ADC32 : BX_INSTR_ADD32);
}
- void
-BX_CPU_C::SBB_EdGd(bxInstruction_c *i)
+void BX_CPU_C::SBB_EdGd(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -228,19 +218,18 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = op1_32 - (op2_32 + temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = op1_32 - (op2_32 + temp_CF);
Write_RMW_virtual_dword(diff_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32,
(temp_CF) ? BX_INSTR_SBB32 : BX_INSTR_SUB32);
}
- void
-BX_CPU_C::SBB_GdEd(bxInstruction_c *i)
+void BX_CPU_C::SBB_GdEd(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -250,10 +239,10 @@
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
- }
+ }
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
- }
+ }
diff_32 = op1_32 - (op2_32 + temp_CF);
@@ -263,8 +252,7 @@
(temp_CF) ? BX_INSTR_SBB32 : BX_INSTR_SUB32);
}
- void
-BX_CPU_C::SBB_EAXId(bxInstruction_c *i)
+void BX_CPU_C::SBB_EAXId(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -280,8 +268,7 @@
(temp_CF) ? BX_INSTR_SBB32 : BX_INSTR_SUB32);
}
- void
-BX_CPU_C::SBB_EdId(bxInstruction_c *i)
+void BX_CPU_C::SBB_EdId(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -293,19 +280,18 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = op1_32 - (op2_32 + temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = op1_32 - (op2_32 + temp_CF);
Write_RMW_virtual_dword(diff_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32,
(temp_CF) ? BX_INSTR_SBB32 : BX_INSTR_SUB32);
}
- void
-BX_CPU_C::SUB_EdGd(bxInstruction_c *i)
+void BX_CPU_C::SUB_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, diff_32;
@@ -315,18 +301,17 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = op1_32 - op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = op1_32 - op2_32;
Write_RMW_virtual_dword(diff_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
}
- void
-BX_CPU_C::SUB_GdEd(bxInstruction_c *i)
+void BX_CPU_C::SUB_GdEd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
unsigned nnn = i->nnn();
@@ -335,10 +320,10 @@
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
- }
+ }
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
- }
+ }
#if defined(BX_HostAsm_Sub32)
Bit32u flags32;
@@ -352,8 +337,7 @@
BX_WRITE_32BIT_REGZ(nnn, diff_32);
}
- void
-BX_CPU_C::SUB_EAXId(bxInstruction_c *i)
+void BX_CPU_C::SUB_EAXId(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
@@ -366,8 +350,7 @@
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
}
- void
-BX_CPU_C::CMP_EdGd(bxInstruction_c *i)
+void BX_CPU_C::CMP_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
@@ -375,10 +358,10 @@
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
- }
+ }
else {
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
- }
+ }
#if defined(BX_HostAsm_Cmp32)
Bit32u flags32;
@@ -390,8 +373,7 @@
#endif
}
- void
-BX_CPU_C::CMP_GdEd(bxInstruction_c *i)
+void BX_CPU_C::CMP_GdEd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
@@ -399,10 +381,10 @@
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
- }
+ }
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
- }
+ }
#if defined(BX_HostAsm_Cmp32)
Bit32u flags32;
@@ -414,8 +396,7 @@
#endif
}
- void
-BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
+void BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
@@ -432,24 +413,22 @@
#endif
}
- void
-BX_CPU_C::CWDE(bxInstruction_c *i)
+void BX_CPU_C::CWDE(bxInstruction_c *i)
{
/* CBW: no flags are effected */
RAX = (Bit16s) AX;
}
- void
-BX_CPU_C::CDQ(bxInstruction_c *i)
+void BX_CPU_C::CDQ(bxInstruction_c *i)
{
/* CDQ: no flags are affected */
if (EAX & 0x80000000) {
RDX = 0xFFFFFFFF;
- }
+ }
else {
RDX = 0x00000000;
- }
+ }
}
// Some info on the opcodes at {0F,A6} and {0F,A7}
@@ -465,22 +444,19 @@
// {OF,B0} = CMPXCHG 8
// {OF,B1} = CMPXCHG 16|32
- void
-BX_CPU_C::CMPXCHG_XBTS(bxInstruction_c *i)
+void BX_CPU_C::CMPXCHG_XBTS(bxInstruction_c *i)
{
BX_INFO(("CMPXCHG_XBTS:"));
UndefinedOpcode(i);
}
- void
-BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i)
+void BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i)
{
BX_INFO(("CMPXCHG_IBTS:"));
UndefinedOpcode(i);
}
- void
-BX_CPU_C::XADD_EdGd(bxInstruction_c *i)
+void BX_CPU_C::XADD_EdGd(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
@@ -503,14 +479,14 @@
// For example: XADD AL, AL
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
sum_32 = op1_32 + op2_32;
Write_RMW_virtual_dword(sum_32);
/* and write destination into source */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
#else
@@ -519,8 +495,7 @@
#endif
}
- void
-BX_CPU_C::ADD_EEdId(bxInstruction_c *i)
+void BX_CPU_C::ADD_EEdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, sum_32;
@@ -540,8 +515,7 @@
Write_RMW_virtual_dword(sum_32);
}
- void
-BX_CPU_C::ADD_EGdId(bxInstruction_c *i)
+void BX_CPU_C::ADD_EGdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, sum_32;
@@ -560,8 +534,7 @@
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
}
- void
-BX_CPU_C::ADC_EdId(bxInstruction_c *i)
+void BX_CPU_C::ADC_EdId(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
@@ -573,19 +546,18 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
sum_32 = op1_32 + op2_32 + temp_CF;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
sum_32 = op1_32 + op2_32 + temp_CF;
Write_RMW_virtual_dword(sum_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32,
(temp_CF) ? BX_INSTR_ADC32 : BX_INSTR_ADD32);
}
- void
-BX_CPU_C::SUB_EdId(bxInstruction_c *i)
+void BX_CPU_C::SUB_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, diff_32;
@@ -595,18 +567,17 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = op1_32 - op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = op1_32 - op2_32;
Write_RMW_virtual_dword(diff_32);
- }
+ }
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
}
- void
-BX_CPU_C::CMP_EdId(bxInstruction_c *i)
+void BX_CPU_C::CMP_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
@@ -614,10 +585,10 @@
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
- }
+ }
else {
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
- }
+ }
#if defined(BX_HostAsm_Cmp32)
Bit32u flags32;
@@ -630,8 +601,7 @@
#endif
}
- void
-BX_CPU_C::NEG_Ed(bxInstruction_c *i)
+void BX_CPU_C::NEG_Ed(bxInstruction_c *i)
{
Bit32u op1_32, diff_32;
@@ -639,19 +609,17 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = -op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = -op1_32;
Write_RMW_virtual_dword(diff_32);
- }
+ }
SET_FLAGS_OSZAPC_RESULT_32(diff_32, BX_INSTR_NEG32);
}
-
- void
-BX_CPU_C::INC_Ed(bxInstruction_c *i)
+void BX_CPU_C::INC_Ed(bxInstruction_c *i)
{
Bit32u op1_32;
@@ -659,19 +627,17 @@
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32++;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32++;
Write_RMW_virtual_dword(op1_32);
- }
+ }
SET_FLAGS_OSZAP_RESULT_32(op1_32, BX_INSTR_INC32);
}
-
- void
-BX_CPU_C::DEC_Ed(bxInstruction_c *i)
+void BX_CPU_C::DEC_Ed(bxInstruction_c *i)
{
Bit32u op1_32;
@@ -689,18 +655,17 @@
SET_FLAGS_OSZAP_RESULT_32(op1_32, BX_INSTR_DEC32);
}
- void
-BX_CPU_C::CMPXCHG_EdGd(bxInstruction_c *i)
+void BX_CPU_C::CMPXCHG_EdGd(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u op2_32, op1_32, diff_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
- }
+ }
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
- }
+ }
diff_32 = EAX - op1_32;
@@ -712,31 +677,30 @@
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
- }
+ }
else {
Write_RMW_virtual_dword(op2_32);
- }
}
+ }
else {
// accumulator <-- dest
RAX = op1_32;
- }
+ }
#else
BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
#endif
}
- void
-BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
+void BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 5) || (BX_CPU_LEVEL_HACKED >= 5)
Bit32u op1_64_lo, op1_64_hi, diff;
if (i->modC0()) {
- BX_INFO(("CMPXCHG8B: dest is reg: #UD"));
+ BX_INFO(("CMPXCHG8B: dest is not memory location (#UD)"));
UndefinedOpcode(i);
- }
+ }
read_virtual_dword(i->seg(), RMAddr(i), &op1_64_lo);
read_RMW_virtual_dword(i->seg(), RMAddr(i) + 4, &op1_64_hi);
@@ -750,14 +714,14 @@
// dest <-- src
Write_RMW_virtual_dword(ECX);
write_virtual_dword(i->seg(), RMAddr(i), &EBX);
- }
+ }
else {
// ZF = 0
set_ZF(0);
// accumulator <-- dest
RAX = op1_64_lo;
RDX = op1_64_hi;
- }
+ }
#else
BX_INFO(("CMPXCHG8B: not supported for cpulevel <= 4"));
Index: arith64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/arith64.cc,v
retrieving revision 1.25
retrieving revision 1.26
diff -u -d -r1.25 -r1.26
--- arith64.cc 2 Apr 2005 18:49:44 -0000 1.25
+++ arith64.cc 19 May 2005 20:25:15 -0000 1.26
@@ -33,633 +33,631 @@
#if BX_SUPPORT_X86_64
- void
-BX_CPU_C::ADD_EqGq(bxInstruction_c *i)
+void BX_CPU_C::ADD_EqGq(bxInstruction_c *i)
{
- /* for 64 bit operand size mode */
- Bit64u op2_64, op1_64, sum_64;
+ /* for 64 bit operand size mode */
+ Bit64u op2_64, op1_64, sum_64;
[...1038 lines suppressed...]
- // accumulator <-- dest
- RAX = op1_64;
- }
+ if (diff == 0) { // if accumulator == dest
+ // ZF = 1
+ set_ZF(1);
+ // dest <-- src
+ Write_RMW_virtual_qword(RCX);
+ write_virtual_qword(i->seg(), RMAddr(i), &RBX);
+ }
+ else {
+ // ZF = 0
+ set_ZF(0);
+ // accumulator <-- dest
+ RAX = op1_64_lo;
+ RDX = op1_64_hi;
+ }
}
#endif /* if BX_SUPPORT_X86_64 */
Index: cpu.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
retrieving revision 1.219
retrieving revision 1.220
diff -u -d -r1.219 -r1.220
--- cpu.h 17 Apr 2005 21:51:58 -0000 1.219
+++ cpu.h 19 May 2005 20:25:15 -0000 1.220
@@ -2439,6 +2439,8 @@
BX_SMF void LOOPE64_Jb(bxInstruction_c *);
BX_SMF void LOOP64_Jb(bxInstruction_c *);
BX_SMF void JCXZ64_Jb(bxInstruction_c *);
+
+ BX_SMF void CMPXCHG16B(bxInstruction_c *);
#endif // #if BX_SUPPORT_X86_64
// mch added
Index: cpuid.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpuid.cc,v
retrieving revision 1.25
retrieving revision 1.26
diff -u -d -r1.25 -r1.26
--- cpuid.cc 20 Apr 2005 18:12:54 -0000 1.25
+++ cpuid.cc 19 May 2005 20:25:16 -0000 1.26
@@ -118,10 +118,14 @@
/* Get CPU extended feature flags. */
Bit32u BX_CPU_C::get_extended_cpuid_features()
{
- Bit32u features = 0; // start with none
+ Bit32u features = 0;
#if BX_SUPPORT_PNI
- features |= 0x01; // report PNI
+ features |= 0x01; // report PNI
+#endif
+
+#if BX_SUPPORT_X86_64
+ features |= (1<<13); // support CMPXCHG16B
#endif
return features;
@@ -130,7 +134,7 @@
/* Get CPU feature flags. Returned by CPUID functions 1 and 80000001. */
Bit32u BX_CPU_C::get_std_cpuid_features()
{
- Bit32u features = 0; // start with none
+ Bit32u features = 0;
#if BX_SUPPORT_FPU
features |= 0x01;
Index: fetchdecode64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/fetchdecode64.cc,v
retrieving revision 1.75
retrieving revision 1.76
diff -u -d -r1.75 -r1.76
--- fetchdecode64.cc 29 Apr 2005 21:28:42 -0000 1.75
+++ fetchdecode64.cc 19 May 2005 20:25:16 -0000 1.76
@@ -435,6 +435,17 @@
/* 7 */ { 0, &BX_CPU_C::BxError }
};
+static BxOpcodeInfo_t BxOpcodeInfo64G9q[8] = {
+ /* 0 */ { 0, &BX_CPU_C::BxError },
+ /* 1 */ { BxLockable, &BX_CPU_C::CMPXCHG16B },
+ /* 2 */ { 0, &BX_CPU_C::BxError },
+ /* 3 */ { 0, &BX_CPU_C::BxError },
+ /* 4 */ { 0, &BX_CPU_C::BxError },
+ /* 5 */ { 0, &BX_CPU_C::BxError },
+ /* 6 */ { 0, &BX_CPU_C::BxError },
+ /* 7 */ { 0, &BX_CPU_C::BxError }
+ };
+
static BxOpcodeInfo_t BxOpcodeInfo64G12[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
@@ -2003,7 +2014,7 @@
/* 0F C4 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
/* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
/* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
- /* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 },
+ /* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9q },
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_RAX },
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_RCX },
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_RDX },
-------------------------------------------------------
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