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List: bochs-cvs
Subject: [Bochs-cvs] CVS: bochs/cpu cpu.h,1.173,1.174 cpuid.cc,1.8,1.9 lazy_flags.cc,1.24,1.25 lazy_flags.h,1
From: Stanislav Shwartsman <sshwarts () users ! sourceforge ! net>
Date: 2004-08-30 21:47:26
Message-ID: E1C1tzq-0000Wf-VN () sc8-pr-cvs1 ! sourceforge ! net
[Download RAW message or body]
Update of /cvsroot/bochs/bochs/cpu
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv1854/cpu
Modified Files:
cpu.h cpuid.cc lazy_flags.cc lazy_flags.h mult16.cc mult32.cc
mult64.cc mult8.cc
Log Message:
Commented problematic check in misc_mem.cc
Implemnted lazy-flags and undocumented flags handling for IMUL instructions
Index: cpu.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
retrieving revision 1.173
retrieving revision 1.174
diff -u -d -r1.173 -r1.174
--- cpu.h 18 Aug 2004 20:47:35 -0000 1.173
+++ cpu.h 30 Aug 2004 21:47:24 -0000 1.174
@@ -3357,7 +3357,6 @@
BX_CPU_THIS_PTR eflags.val32 &= ~((1<<11) | (1<<0)); \
BX_CPU_THIS_PTR eflags.val32 |= ((!!new_of)<<11) | ((!!new_cf)<<0); \
BX_CPU_THIS_PTR lf_flags_status &= 0x0ffff0; \
- /* could also mark other bits undefined here ? */ \
}
#endif // #ifndef BX_CPU_H
Index: cpuid.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/cpuid.cc,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- cpuid.cc 27 Aug 2004 18:43:23 -0000 1.8
+++ cpuid.cc 30 Aug 2004 21:47:24 -0000 1.9
@@ -122,7 +122,7 @@
{
Bit32u features = 0; // start with none
- // EAX: CPU Version Infromation
+ // EAX: CPU Version Information
// [3:0] Stepping ID
// [7:4] Model: starts at 1
// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
@@ -285,8 +285,8 @@
// [22:22] AMD MMX Extensions
// [25:28] Reserved
// [29:29] Long Mode
- // [30:30] AMD 3DNow Extensions
- // [31:31] AMD 3DNow Intructions
+ // [30:30] AMD 3DNow! Extensions
+ // [31:31] AMD 3DNow! Instructions
features = features & 0x0183F3FF;
RDX = features | (1 << 29) | (1 << 11);
RBX = 0;
Index: lazy_flags.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/lazy_flags.cc,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -d -r1.24 -r1.25
--- lazy_flags.cc 27 Aug 2004 18:43:23 -0000 1.24
+++ lazy_flags.cc 30 Aug 2004 21:47:24 -0000 1.25
@@ -31,7 +31,6 @@
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
-
bx_bool BX_CPU_C::get_CFLazy(void)
{
unsigned cf;
@@ -228,17 +227,46 @@
(64 - BX_CPU_THIS_PTR oszapc.op2_64)) & 0x01;
break;
#endif
- case BX_INSTR_MUL8:
+ case BX_INSTR_IMUL_AL:
+ cf = ! ((BX_CPU_THIS_PTR oszapc.op1_8 < 0x80 &&
+ BX_CPU_THIS_PTR oszapc.op2_8 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_8 & 0x80) &&
+ BX_CPU_THIS_PTR oszapc.op2_8 == 0xff));
+ break;
+ case BX_INSTR_IMUL16:
+ case BX_INSTR_IMUL_AX:
+ cf = ! ((BX_CPU_THIS_PTR oszapc.op1_16 < 0x8000 &&
+ BX_CPU_THIS_PTR oszapc.op2_16 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_16 & 0x8000) &&
+ BX_CPU_THIS_PTR oszapc.op2_16 == 0xffff));
+ break;
+ case BX_INSTR_IMUL32:
+ case BX_INSTR_IMUL_EAX:
+ cf = ! ((BX_CPU_THIS_PTR oszapc.op1_32 < 0x80000000 &&
+ BX_CPU_THIS_PTR oszapc.op2_32 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_32 & 0x80000000) &&
+ BX_CPU_THIS_PTR oszapc.op2_32 == 0xffffffff));
+ break;
+#if BX_SUPPORT_X86_64
+ case BX_INSTR_IMUL64:
+ case BX_INSTR_IMUL_RAX:
+ cf = ! ((BX_CPU_THIS_PTR oszapc.op1_64 < BX_CONST64(0x8000000000000000) &&
+ BX_CPU_THIS_PTR oszapc.op2_64 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_64 & BX_CONST64(0x8000000000000000)) &&
+ BX_CPU_THIS_PTR oszapc.op2_64 == BX_CONST64(0xffffffffffffffff)));
+ break;
+#endif
+ case BX_INSTR_MUL_AL:
cf = (BX_CPU_THIS_PTR oszapc.op2_8 != 0);
break;
- case BX_INSTR_MUL16:
+ case BX_INSTR_MUL_AX:
cf = (BX_CPU_THIS_PTR oszapc.op2_16 != 0);
break;
- case BX_INSTR_MUL32:
+ case BX_INSTR_MUL_EAX:
cf = (BX_CPU_THIS_PTR oszapc.op2_32 != 0);
break;
#if BX_SUPPORT_X86_64
- case BX_INSTR_MUL64:
+ case BX_INSTR_MUL_RAX:
cf = (BX_CPU_THIS_PTR oszapc.op2_64 != 0);
break;
#endif
@@ -332,7 +360,9 @@
case BX_INSTR_SAR64:
case BX_INSTR_SHR64:
case BX_INSTR_SHL64:
- case BX_INSTR_MUL64:
+ case BX_INSTR_IMUL_RAX:
+ case BX_INSTR_IMUL64:
+ case BX_INSTR_MUL_RAX:
#endif
case BX_INSTR_SAR8:
case BX_INSTR_SAR16:
@@ -343,9 +373,14 @@
case BX_INSTR_SHL8:
case BX_INSTR_SHL16:
case BX_INSTR_SHL32:
- case BX_INSTR_MUL8:
- case BX_INSTR_MUL16:
- case BX_INSTR_MUL32:
+ case BX_INSTR_IMUL16:
+ case BX_INSTR_IMUL32:
+ case BX_INSTR_IMUL_AL:
+ case BX_INSTR_IMUL_AX:
+ case BX_INSTR_IMUL_EAX:
+ case BX_INSTR_MUL_AL:
+ case BX_INSTR_MUL_AX:
+ case BX_INSTR_MUL_EAX:
af = 0;
break;
default:
@@ -461,24 +496,39 @@
zf = (BX_CPU_THIS_PTR oszapc.result_64 == 0);
break;
#endif
- case BX_INSTR_MUL8:
+ case BX_INSTR_IMUL_AL:
+ case BX_INSTR_MUL_AL:
zf = (BX_CPU_THIS_PTR oszapc.op1_8 |
BX_CPU_THIS_PTR oszapc.op2_8) == 0;
break;
- case BX_INSTR_MUL16:
+ case BX_INSTR_IMUL_AX:
+ case BX_INSTR_MUL_AX:
zf = (BX_CPU_THIS_PTR oszapc.op1_16 |
BX_CPU_THIS_PTR oszapc.op2_16) == 0;
break;
- case BX_INSTR_MUL32:
+ case BX_INSTR_IMUL_EAX:
+ case BX_INSTR_MUL_EAX:
zf = (BX_CPU_THIS_PTR oszapc.op1_32 |
BX_CPU_THIS_PTR oszapc.op2_32) == 0;
break;
#if BX_SUPPORT_X86_64
- case BX_INSTR_MUL64:
+ case BX_INSTR_IMUL_RAX:
+ case BX_INSTR_MUL_RAX:
zf = (BX_CPU_THIS_PTR oszapc.op1_64 |
BX_CPU_THIS_PTR oszapc.op2_64) == 0;
break;
#endif
+ case BX_INSTR_IMUL16:
+ zf = (BX_CPU_THIS_PTR oszapc.op1_16 == 0);
+ break;
+ case BX_INSTR_IMUL32:
+ zf = (BX_CPU_THIS_PTR oszapc.op1_32 == 0);
+ break;
+#if BX_SUPPORT_X86_64
+ case BX_INSTR_IMUL64:
+ zf = (BX_CPU_THIS_PTR oszapc.op1_64 == 0);
+ break;
+#endif
case BX_INSTR_BITSCAN16:
case BX_INSTR_BITSCAN32:
#if BX_SUPPORT_X86_64
@@ -590,20 +640,35 @@
sf = (BX_CPU_THIS_PTR oszapc.result_64 >= BX_CONST64(0x8000000000000000));
break;
#endif
- case BX_INSTR_MUL8:
+ case BX_INSTR_IMUL_AL:
+ case BX_INSTR_MUL_AL:
sf = (BX_CPU_THIS_PTR oszapc.op2_8 >= 0x80);
break;
- case BX_INSTR_MUL16:
+ case BX_INSTR_IMUL_AX:
+ case BX_INSTR_MUL_AX:
sf = (BX_CPU_THIS_PTR oszapc.op2_16 >= 0x8000);
break;
- case BX_INSTR_MUL32:
+ case BX_INSTR_IMUL_EAX:
+ case BX_INSTR_MUL_EAX:
sf = (BX_CPU_THIS_PTR oszapc.op2_32 >= 0x80000000);
break;
#if BX_SUPPORT_X86_64
- case BX_INSTR_MUL64:
+ case BX_INSTR_IMUL_RAX:
+ case BX_INSTR_MUL_RAX:
sf = (BX_CPU_THIS_PTR oszapc.op2_64 >= BX_CONST64(0x8000000000000000));
break;
#endif
+ case BX_INSTR_IMUL16:
+ sf = (BX_CPU_THIS_PTR oszapc.op1_16 >= 0x8000);
+ break;
+ case BX_INSTR_IMUL32:
+ sf = (BX_CPU_THIS_PTR oszapc.op1_32 >= 0x80000000);
+ break;
+#if BX_SUPPORT_X86_64
+ case BX_INSTR_IMUL64:
+ sf = (BX_CPU_THIS_PTR oszapc.op1_64 >= BX_CONST64(0x8000000000000000));
+ break;
+#endif
default:
sf = 0; // Keep compiler quiet.
BX_PANIC(("get_SF: OSZAPC: unknown instr"));
@@ -818,17 +883,46 @@
BX_CPU_THIS_PTR oszapc.result_64) & BX_CONST64(0x8000000000000000)) > 0;
break;
#endif
- case BX_INSTR_MUL8:
+ case BX_INSTR_IMUL_AL:
+ of = ! ((BX_CPU_THIS_PTR oszapc.op1_8 < 0x80 &&
+ BX_CPU_THIS_PTR oszapc.op2_8 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_8 & 0x80) &&
+ BX_CPU_THIS_PTR oszapc.op2_8 == 0xff));
+ break;
+ case BX_INSTR_IMUL16:
+ case BX_INSTR_IMUL_AX:
+ of = ! ((BX_CPU_THIS_PTR oszapc.op1_16 < 0x8000 &&
+ BX_CPU_THIS_PTR oszapc.op2_16 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_16 & 0x8000) &&
+ BX_CPU_THIS_PTR oszapc.op2_16 == 0xffff));
+ break;
+ case BX_INSTR_IMUL32:
+ case BX_INSTR_IMUL_EAX:
+ of = ! ((BX_CPU_THIS_PTR oszapc.op1_32 < 0x80000000 &&
+ BX_CPU_THIS_PTR oszapc.op2_32 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_32 & 0x80000000) &&
+ BX_CPU_THIS_PTR oszapc.op2_32 == 0xffffffff));
+ break;
+#if BX_SUPPORT_X86_64
+ case BX_INSTR_IMUL64:
+ case BX_INSTR_IMUL_RAX:
+ of = ! ((BX_CPU_THIS_PTR oszapc.op1_64 < BX_CONST64(0x8000000000000000) &&
+ BX_CPU_THIS_PTR oszapc.op2_64 == 0) ||
+ ((BX_CPU_THIS_PTR oszapc.op1_64 & BX_CONST64(0x8000000000000000)) &&
+ BX_CPU_THIS_PTR oszapc.op2_64 == BX_CONST64(0xffffffffffffffff)));
+ break;
+#endif
+ case BX_INSTR_MUL_AL:
of = (BX_CPU_THIS_PTR oszapc.op2_8 != 0);
break;
- case BX_INSTR_MUL16:
+ case BX_INSTR_MUL_AX:
of = (BX_CPU_THIS_PTR oszapc.op2_16 != 0);
break;
- case BX_INSTR_MUL32:
+ case BX_INSTR_MUL_EAX:
of = (BX_CPU_THIS_PTR oszapc.op2_32 != 0);
break;
#if BX_SUPPORT_X86_64
- case BX_INSTR_MUL64:
+ case BX_INSTR_MUL_RAX:
of = (BX_CPU_THIS_PTR oszapc.op2_64 != 0);
break;
#endif
@@ -946,17 +1040,24 @@
pf = bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.result_64];
break;
#endif
- case BX_INSTR_MUL8:
+ case BX_INSTR_IMUL_AL:
+ case BX_INSTR_MUL_AL:
pf = bx_parity_lookup[BX_CPU_THIS_PTR oszapc.op1_8];
break;
- case BX_INSTR_MUL16:
+ case BX_INSTR_IMUL_AX:
+ case BX_INSTR_IMUL16:
+ case BX_INSTR_MUL_AX:
pf = bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.op1_16];
break;
- case BX_INSTR_MUL32:
- pf = bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.op1_16];
+ case BX_INSTR_IMUL_EAX:
+ case BX_INSTR_IMUL32:
+ case BX_INSTR_MUL_EAX:
+ pf = bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.op1_32];
break;
#if BX_SUPPORT_X86_64
- case BX_INSTR_MUL64:
+ case BX_INSTR_IMUL_RAX:
+ case BX_INSTR_IMUL64:
+ case BX_INSTR_MUL_RAX:
pf = bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.op1_64];
break;
#endif
Index: lazy_flags.h
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/lazy_flags.h,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- lazy_flags.h 26 Aug 2004 20:37:50 -0000 1.16
+++ lazy_flags.h 30 Aug 2004 21:47:24 -0000 1.17
@@ -94,10 +94,21 @@
#define BX_INSTR_SAR32 51
#define BX_INSTR_SAR64 52
-#define BX_INSTR_MUL8 53
-#define BX_INSTR_MUL16 54
-#define BX_INSTR_MUL32 55
-#define BX_INSTR_MUL64 56
+#define BX_INSTR_MUL_AL 53
+#define BX_INSTR_MUL_AX 54
+#define BX_INSTR_MUL_EAX 55
+#define BX_INSTR_MUL_RAX 56
+
+#define BX_INSTR_IMUL_AL 57
+#define BX_INSTR_IMUL_AX 58
+#define BX_INSTR_IMUL_EAX 59
+#define BX_INSTR_IMUL_RAX 60
+
+// BX_INSTR_IMUL8 not exists, leave number for alignment
+#define BX_INSTR_IMUL16 62
+#define BX_INSTR_IMUL32 63
+#define BX_INSTR_IMUL64 64
+
#define BX_LF_INDEX_OSZAPC 1
#define BX_LF_INDEX_OSZAP 2
Index: mult16.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/mult16.cc,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- mult16.cc 26 Aug 2004 20:37:50 -0000 1.15
+++ mult16.cc 30 Aug 2004 21:47:24 -0000 1.16
@@ -51,7 +51,7 @@
Bit16u product_16h = product_32 >> 16;
/* set EFLAGS */
- SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_MUL16);
+ SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_MUL_AX);
/* now write product back to destination */
AX = product_16l;
@@ -62,8 +62,6 @@
BX_CPU_C::IMUL_AXEw(bxInstruction_c *i)
{
Bit16s op1_16, op2_16;
- Bit32s product_32;
- Bit16u product_16h, product_16l;
op1_16 = AX;
@@ -76,29 +74,19 @@
read_virtual_word(i->seg(), RMAddr(i), (Bit16u *) &op2_16);
}
- product_32 = ((Bit32s) op1_16) * ((Bit32s) op2_16);
- product_16l = (product_32 & 0xFFFF);
- product_16h = product_32 >> 16;
+ Bit32s product_32 = ((Bit32s) op1_16) * ((Bit32s) op2_16);
+ Bit16u product_16l = (product_32 & 0xFFFF);
+ Bit16u product_16h = product_32 >> 16;
/* now write product back to destination */
AX = product_16l;
DX = product_16h;
/* set eflags:
- * IMUL affects the following flags: C,O
* IMUL r/m16: condition for clearing CF & OF:
* DX:AX = sign-extend of AX
*/
-
- if ( (DX==0xffff) && (AX & 0x8000) ) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else if ( (DX==0x0000) && (AX < 0x8000) ) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_IMUL_AX);
}
void
@@ -189,9 +177,7 @@
void
BX_CPU_C::IMUL_GwEwIw(bxInstruction_c *i)
{
- Bit16u product_16l;
Bit16s op2_16, op3_16;
- Bit32s product_32;
op3_16 = i->Iw();
@@ -204,32 +190,24 @@
read_virtual_word(i->seg(), RMAddr(i), (Bit16u *) &op2_16);
}
- product_32 = op2_16 * op3_16;
- product_16l = (product_32 & 0xFFFF);
+ Bit32s product_32 = op2_16 * op3_16;
+ Bit16u product_16l = (product_32 & 0xFFFF);
+ Bit16u product_16h = (product_32 >> 16);
/* now write product back to destination */
BX_WRITE_16BIT_REG(i->nnn(), product_16l);
/* set eflags:
- * IMUL affects the following flags: C,O
* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
* result exactly fits within r16
*/
-
- if (product_32 > -32768 && product_32 < 32767) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_IMUL16);
}
void
BX_CPU_C::IMUL_GwEw(bxInstruction_c *i)
{
- Bit16u product_16l;
Bit16s op1_16, op2_16;
- Bit32s product_32;
/* op2 is a register or memory reference */
if (i->modC0()) {
@@ -242,22 +220,16 @@
op1_16 = BX_READ_16BIT_REG(i->nnn());
- product_32 = op1_16 * op2_16;
- product_16l = (product_32 & 0xFFFF);
+ Bit32s product_32 = op1_16 * op2_16;
+ Bit16u product_16l = (product_32 & 0xFFFF);
+ Bit16u product_16h = (product_32 >> 16);
/* now write product back to destination */
BX_WRITE_16BIT_REG(i->nnn(), product_16l);
/* set eflags:
- * IMUL affects the following flags: C,O
* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
* result exactly fits within r16
*/
-
- if (product_32 > -32768 && product_32 < 32767) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_IMUL16);
}
Index: mult32.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/mult32.cc,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- mult32.cc 26 Aug 2004 20:37:50 -0000 1.15
+++ mult32.cc 30 Aug 2004 21:47:24 -0000 1.16
@@ -59,7 +59,7 @@
product_32h = (Bit32u) (product_64 >> 32);
/* set EFLAGS */
- SET_FLAGS_OSZAPC_S1S2_32(product_32l, product_32h, BX_INSTR_MUL32);
+ SET_FLAGS_OSZAPC_S1S2_32(product_32l, product_32h, BX_INSTR_MUL_EAX);
/* now write product back to destination */
RAX = product_32l;
@@ -70,8 +70,6 @@
BX_CPU_C::IMUL_EAXEd(bxInstruction_c *i)
{
Bit32s op1_32, op2_32;
- Bit64s product_64;
- Bit32u product_32h, product_32l;
op1_32 = EAX;
@@ -84,29 +82,19 @@
read_virtual_dword(i->seg(), RMAddr(i), (Bit32u *) &op2_32);
}
- product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
- product_32l = (Bit32u) (product_64 & 0xFFFFFFFF);
- product_32h = (Bit32u) (product_64 >> 32);
+ Bit64s product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
+ Bit32u product_32l = (Bit32u) (product_64 & 0xFFFFFFFF);
+ Bit32u product_32h = (Bit32u) (product_64 >> 32);
/* now write product back to destination */
RAX = product_32l;
RDX = product_32h;
/* set eflags:
- * IMUL affects the following flags: C,O
- * IMUL r/m16: condition for clearing CF & OF:
+ * IMUL r/m32: condition for clearing CF & OF:
* EDX:EAX = sign-extend of EAX
*/
-
- if ( (EDX==0xffffffff) && (EAX & 0x80000000) ) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else if ( (EDX==0x00000000) && (EAX < 0x80000000) ) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_32(product_32l, product_32h, BX_INSTR_IMUL_EAX);
}
void
@@ -193,8 +181,7 @@
void
BX_CPU_C::IMUL_GdEdId(bxInstruction_c *i)
{
- Bit32s op2_32, op3_32, product_32;
- Bit64s product_64;
+ Bit32s op2_32, op3_32;
op3_32 = i->Id();
@@ -207,32 +194,24 @@
read_virtual_dword(i->seg(), RMAddr(i), (Bit32u *) &op2_32);
}
- product_32 = op2_32 * op3_32;
- product_64 = ((Bit64s) op2_32) * ((Bit64s) op3_32);
+ Bit64s product_64 = ((Bit64s) op2_32) * ((Bit64s) op3_32);
+ Bit32u product_32l = (product_64 & 0xFFFFFFFF);
+ Bit32u product_32h = (product_64 >> 32);
/* now write product back to destination */
- BX_WRITE_32BIT_REGZ(i->nnn(), product_32);
+ BX_WRITE_32BIT_REGZ(i->nnn(), product_32l);
/* set eflags:
- * IMUL affects the following flags: C,O
- * IMUL r16,r/m16,imm16: condition for clearing CF & OF:
- * result exactly fits within r16
+ * IMUL r32,r/m32,imm32: condition for clearing CF & OF:
+ * result exactly fits within r32
*/
-
- if (product_64 == product_32) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_32(product_32l, product_32h, BX_INSTR_IMUL32);
}
-
void
BX_CPU_C::IMUL_GdEd(bxInstruction_c *i)
{
- Bit32s op1_32, op2_32, product_32;
- Bit64s product_64;
+ Bit32s op1_32, op2_32;
/* op2 is a register or memory reference */
if (i->modC0()) {
@@ -245,22 +224,16 @@
op1_32 = BX_READ_32BIT_REG(i->nnn());
- product_32 = op1_32 * op2_32;
- product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
+ Bit64s product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
+ Bit32u product_32l = (product_64 & 0xFFFFFFFF);
+ Bit32u product_32h = (product_64 >> 32);
/* now write product back to destination */
- BX_WRITE_32BIT_REGZ(i->nnn(), product_32);
+ BX_WRITE_32BIT_REGZ(i->nnn(), product_32l);
/* set eflags:
- * IMUL affects the following flags: C,O
- * IMUL r16,r/m16,imm16: condition for clearing CF & OF:
- * result exactly fits within r16
+ * IMUL r32,r/m32,imm32: condition for clearing CF & OF:
+ * result exactly fits within r32
*/
-
- if (product_64 == product_32) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_32(product_32l, product_32h, BX_INSTR_IMUL32);
}
Index: mult64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/mult64.cc,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- mult64.cc 26 Aug 2004 20:37:50 -0000 1.12
+++ mult64.cc 30 Aug 2004 21:47:24 -0000 1.13
@@ -229,7 +229,7 @@
long_mul(&product_128,op1_64,op2_64);
/* set EFLAGS */
- SET_FLAGS_OSZAPC_S1S2_64(product_128.lo, product_128.hi, BX_INSTR_MUL64);
+ SET_FLAGS_OSZAPC_S1S2_64(product_128.lo, product_128.hi, BX_INSTR_MUL_RAX);
/* now write product back to destination */
RAX = product_128.lo;
@@ -264,20 +264,10 @@
RDX = product_128.hi;
/* set eflags:
- * IMUL affects the following flags: C,O
- * IMUL r/m16: condition for clearing CF & OF:
+ * IMUL r/m64: condition for clearing CF & OF:
* RDX:RAX = sign-extend of RAX
*/
-
- if ( (RDX==BX_CONST64(0xffffffffffffffff)) && (RAX & BX_CONST64(0x8000000000000000)) ) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else if ( (RDX==BX_CONST64(0x0000000000000000)) && (RAX < BX_CONST64(0x8000000000000000)) ) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_64(product_128.lo, product_128.hi, BX_INSTR_IMUL_RAX);
}
void
@@ -370,7 +360,7 @@
void
BX_CPU_C::IMUL_GqEqId(bxInstruction_c *i)
{
- Bit64s op2_64, op3_64, product_64;
+ Bit64s op2_64, op3_64;
Bit128s product_128;
op3_64 = (Bit32s) i->Id();
@@ -384,30 +374,22 @@
read_virtual_qword(i->seg(), RMAddr(i), (Bit64u *) &op2_64);
}
- product_64 = op2_64 * op3_64;
long_imul(&product_128,op2_64,op3_64);
/* now write product back to destination */
- BX_WRITE_64BIT_REG(i->nnn(), product_64);
+ BX_WRITE_64BIT_REG(i->nnn(), product_128.lo);
/* set eflags:
- * IMUL affects the following flags: C,O
- * IMUL r16,r/m16,imm16: condition for clearing CF & OF:
- * result exactly fits within r16
+ * IMUL r64,r/m64,imm64: condition for clearing CF & OF:
+ * result exactly fits within r64
*/
-
- if (product_128.lo == product_64) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_64(product_128.lo, product_128.hi, BX_INSTR_IMUL64);
}
void
BX_CPU_C::IMUL_GqEq(bxInstruction_c *i)
{
- Bit64s op1_64, op2_64, product_64;
+ Bit64s op1_64, op2_64;
Bit128s product_128;
/* op2 is a register or memory reference */
@@ -421,24 +403,16 @@
op1_64 = BX_READ_64BIT_REG(i->nnn());
- product_64 = op1_64 * op2_64;
long_imul(&product_128,op1_64,op2_64);
/* now write product back to destination */
- BX_WRITE_64BIT_REG(i->nnn(), product_64);
+ BX_WRITE_64BIT_REG(i->nnn(), product_128.lo);
/* set eflags:
- * IMUL affects the following flags: C,O
- * IMUL r16,r/m16,imm16: condition for clearing CF & OF:
- * result exactly fits within r16
+ * IMUL r64,r/m64,imm64: condition for clearing CF & OF:
+ * result exactly fits within r64
*/
-
- if (product_128.lo == product_64) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_64(product_128.lo, product_128.hi, BX_INSTR_IMUL64);
}
#endif /* if BX_SUPPORT_X86_64 */
Index: mult8.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/mult8.cc,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- mult8.cc 26 Aug 2004 20:37:50 -0000 1.15
+++ mult8.cc 30 Aug 2004 21:47:24 -0000 1.16
@@ -52,7 +52,7 @@
Bit8u product_8h = product_16 >> 8;
/* set EFLAGS */
- SET_FLAGS_OSZAPC_S1S2_8(product_8l, product_8h, BX_INSTR_MUL8);
+ SET_FLAGS_OSZAPC_S1S2_8(product_8l, product_8h, BX_INSTR_MUL_AL);
/* now write product back to destination */
AX = product_16;
@@ -76,21 +76,17 @@
Bit16s product_16 = op1 * op2;
- /* now write product back to destination */
- AX = product_16;
+ Bit8u product_8l = (product_16 & 0xFF);
+ Bit8u product_8h = product_16 >> 8;
/* set EFLAGS:
- * IMUL affects the following flags: C,O
* IMUL r/m8: condition for clearing CF & OF:
* AL = sign-extend of AL to 16 bits
*/
- Bit16u upper_bits = AX & 0xff80;
- if (upper_bits==0xff80 || upper_bits==0x0000) {
- SET_FLAGS_OxxxxC(0, 0);
- }
- else {
- SET_FLAGS_OxxxxC(1, 1);
- }
+ SET_FLAGS_OSZAPC_S1S2_8(product_8l, product_8h, BX_INSTR_IMUL_AL);
+
+ /* now write product back to destination */
+ AX = product_16;
}
void
-------------------------------------------------------
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