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List: bochs-cvs
Subject: [Bochs-cvs] CVS: bochs/cpu shift16.cc,1.22,1.23 shift32.cc,1.23,1.24 shift64.cc,1.14,1.15 shift8.cc,
From: Stanislav Shwartsman <sshwarts () users ! sourceforge ! net>
Date: 2004-08-27 20:13:35
Message-ID: E1C0n6N-0005aK-8a () sc8-pr-cvs1 ! sourceforge ! net
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Update of /cvsroot/bochs/bochs/cpu
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv21279/cpu
Modified Files:
shift16.cc shift32.cc shift64.cc shift8.cc
Log Message:
Fixed flags handling for SHLD and rotate instrructions
Index: shift16.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/shift16.cc,v
retrieving revision 1.22
retrieving revision 1.23
diff -u -d -r1.22 -r1.23
--- shift16.cc 15 Aug 2004 20:31:27 -0000 1.22
+++ shift16.cc 27 Aug 2004 20:13:32 -0000 1.23
@@ -58,7 +58,7 @@
}
op2_16 = BX_READ_16BIT_REG(i->nnn());
- temp_32 = (op1_16 << 16) | (op2_16); // double formed by op1:op2
+ temp_32 = ((Bit32u)(op1_16) << 16) | (op2_16); // double formed by op1:op2
result_32 = temp_32 << count;
if (count > 16) {
// hack to act like x86 SHLD when count > 16
@@ -81,6 +81,7 @@
set_CF( (temp_32 >> (32 - count)) & 0x01 );
if (count == 1)
set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
+ set_AF(0);
set_ZF(result_16 == 0);
set_SF(result_16 >> 15);
set_PF_base((Bit8u) result_16);
@@ -142,6 +143,7 @@
set_CF((temp_32 >> (count - 1)) & 0x01);
set_ZF(result_16 == 0);
set_SF(result_16 >> 15);
+ set_AF(0);
/* for shift of 1, OF set if sign change occurred. */
if (count == 1)
set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
@@ -174,8 +176,9 @@
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
- if (count) {
- result_16 = (op1_16 << count) | (op1_16 >> (16 - count));
+ if (! count) return;
+
+ result_16 = (op1_16 << count) | (op1_16 >> (16 - count));
/* now write result back to destination */
if (i->modC0()) {
@@ -186,19 +189,18 @@
}
/* set eflags:
- * ROL count affects the following flags: C
+ * ROL count affects the following flags: C, O
*/
+ bx_bool temp_CF = (result_16 & 0x01);
- set_CF(result_16 & 0x01);
- if (count == 1)
- set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
- }
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_16 >> 15));
}
void
BX_CPU_C::ROR_Ew(bxInstruction_c *i)
{
- Bit16u op1_16, result_16, result_b15;
+ Bit16u op1_16, result_16;
unsigned count;
if ( i->b1() == 0xc1 )
@@ -219,8 +221,9 @@
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
- if (count) {
- result_16 = (op1_16 >> count) | (op1_16 << (16 - count));
+ if (! count) return;
+
+ result_16 = (op1_16 >> count) | (op1_16 << (16 - count));
/* now write result back to destination */
if (i->modC0()) {
@@ -231,14 +234,13 @@
}
/* set eflags:
- * ROR count affects the following flags: C
+ * ROR count affects the following flags: C, O
*/
- result_b15 = result_16 & 0x8000;
+ bx_bool result_b15 = (result_16 & 0x8000) != 0;
- set_CF(result_b15 != 0);
+ set_CF(result_b15);
if (count == 1)
set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
- }
}
void
@@ -255,6 +257,7 @@
count = CL;
count &= 0x1F;
+ count %= 17;
/* op1 is a register or memory reference */
if (i->modC0()) {
@@ -265,8 +268,6 @@
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
- count %= 17;
-
if (!count) return;
if (count==1) {
@@ -291,15 +292,14 @@
}
/* set eflags:
- * RCL count affects the following flags: C
+ * RCL count affects the following flags: C, O
*/
+ bx_bool temp_CF = (op1_16 >> (16 - count)) & 0x01;
- if (count == 1)
- set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
- set_CF((op1_16 >> (16 - count)) & 0x01);
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_16 >> 15));
}
-
void
BX_CPU_C::RCR_Ew(bxInstruction_c *i)
{
@@ -314,6 +314,7 @@
count = CL;
count = count & 0x1F;
+ count %= 17;
/* op1 is a register or memory reference */
if (i->modC0()) {
@@ -324,8 +325,8 @@
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
- count %= 17;
- if (count) {
+ if (! count) return;
+
result_16 = (op1_16 >> count) |
(getB_CF() << (16 - count)) |
(op1_16 << (17 - count));
@@ -339,16 +340,14 @@
}
/* set eflags:
- * RCR count affects the following flags: C
+ * RCR count affects the following flags: C, O
*/
set_CF((op1_16 >> (count - 1)) & 0x01);
if (count == 1)
set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
- }
}
-
void
BX_CPU_C::SHL_Ew(bxInstruction_c *i)
{
Index: shift32.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/shift32.cc,v
retrieving revision 1.23
retrieving revision 1.24
diff -u -d -r1.23 -r1.24
--- shift32.cc 15 Aug 2004 20:31:27 -0000 1.23
+++ shift32.cc 27 Aug 2004 20:13:32 -0000 1.24
@@ -71,6 +71,7 @@
set_CF((op1_32 >> (32 - count)) & 0x01);
if (count == 1)
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
+ set_AF(0);
set_ZF(result_32 == 0);
set_PF_base(result_32);
set_SF(result_32 >> 31);
@@ -121,6 +122,7 @@
set_CF((op1_32 >> (count - 1)) & 0x01);
set_ZF(result_32 == 0);
set_SF(result_32 >> 31);
+ set_AF(0);
/* for shift of 1, OF set if sign change occurred. */
if (count == 1)
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
@@ -151,7 +153,8 @@
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
- if (count) {
+ if (! count) return;
+
result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
/* now write result back to destination */
@@ -163,19 +166,18 @@
}
/* set eflags:
- * ROL count affects the following flags: C
+ * ROL count affects the following flags: C, O
*/
+ bx_bool temp_CF = (result_32 & 0x01);
- set_CF(result_32 & 0x01);
- if (count == 1)
- set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
- }
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_32 >> 31));
}
void
BX_CPU_C::ROR_Ed(bxInstruction_c *i)
{
- Bit32u op1_32, result_32, result_b31;
+ Bit32u op1_32, result_32;
unsigned count;
if (i->b1() == 0xc1)
@@ -194,7 +196,8 @@
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
- if (count) {
+ if (! count) return;
+
result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
/* now write result back to destination */
@@ -206,14 +209,13 @@
}
/* set eflags:
- * ROR count affects the following flags: C
+ * ROR count affects the following flags: C, O
*/
- result_b31 = result_32 & 0x80000000;
+ bx_bool result_b31 = (result_32 & 0x80000000) != 0;
- set_CF(result_b31 != 0);
+ set_CF(result_b31);
if (count == 1)
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
- }
}
void
@@ -258,13 +260,13 @@
}
/* set eflags:
- * RCL count affects the following flags: C
+ * RCL count affects the following flags: C, O
*/
- if (count == 1)
- set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
- set_CF((op1_32 >> (32 - count)) & 0x01);
-}
+ bx_bool temp_CF = (op1_32 >> (32 - count)) & 0x01;
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_32 >> 31));
+}
void
BX_CPU_C::RCR_Ed(bxInstruction_c *i)
@@ -308,7 +310,7 @@
}
/* set eflags:
- * RCR count affects the following flags: C
+ * RCR count affects the following flags: C, O
*/
set_CF((op1_32 >> (count - 1)) & 0x01);
Index: shift64.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/shift64.cc,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- shift64.cc 15 Aug 2004 20:31:27 -0000 1.14
+++ shift64.cc 27 Aug 2004 20:13:32 -0000 1.15
@@ -73,6 +73,7 @@
set_CF((op1_64 >> (64 - count)) & 0x01);
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
+ set_AF(0);
set_ZF(result_64 == 0);
set_PF_base(result_64);
set_SF(result_64 >> 63);
@@ -118,6 +119,7 @@
set_CF((op1_64 >> (count - 1)) & 0x01);
set_ZF(result_64 == 0);
set_SF(result_64 >> 63);
+ set_AF(0);
/* for shift of 1, OF set if sign change occurred. */
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
@@ -146,7 +148,8 @@
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
- if (count) {
+ if (! count) return;
+
result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
/* now write result back to destination */
@@ -158,19 +161,18 @@
}
/* set eflags:
- * ROL count affects the following flags: C
+ * ROL count affects the following flags: C, O
*/
+ bx_bool temp_CF = (result_64 & 0x01);
- set_CF(result_64 & 0x01);
- if (count == 1)
- set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
- }
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_64 >> 63));
}
void
BX_CPU_C::ROR_Eq(bxInstruction_c *i)
{
- Bit64u op1_64, result_64, result_b63;
+ Bit64u op1_64, result_64;
unsigned count;
if (i->b1() == 0xc1)
@@ -189,7 +191,8 @@
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
- if (count) {
+ if (! count) return;
+
result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
/* now write result back to destination */
@@ -201,14 +204,13 @@
}
/* set eflags:
- * ROR count affects the following flags: C
+ * ROR count affects the following flags: C, O
*/
- result_b63 = result_64 & BX_CONST64(0x8000000000000000);
+ bx_bool result_b63 = (result_64 & BX_CONST64(0x8000000000000000)) != 0;
- set_CF(result_b63 != 0);
+ set_CF(result_b63);
if (count == 1)
set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
- }
}
void
@@ -253,11 +255,12 @@
}
/* set eflags:
- * RCL count affects the following flags: C
+ * RCL count affects the following flags: C, O
*/
- if (count == 1)
- set_OF(((op1_64 ^ result_64) & BX_CONST64(0x8000000000000000)) > 0);
- set_CF((op1_64 >> (64 - count)) & 0x01);
+ bx_bool temp_CF = (op1_64 >> (64 - count)) & 0x01;
+
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_64 >> 63));
}
void
@@ -302,7 +305,7 @@
}
/* set eflags:
- * RCR count affects the following flags: C
+ * RCR count affects the following flags: C, O
*/
set_CF((op1_64 >> (count - 1)) & 0x01);
Index: shift8.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/shift8.cc,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- shift8.cc 15 Aug 2004 20:31:27 -0000 1.17
+++ shift8.cc 27 Aug 2004 20:13:32 -0000 1.18
@@ -54,7 +54,8 @@
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
- if (count) {
+ if (! count) return;
+
result_8 = (op1_8 << count) | (op1_8 >> (8 - count));
/* now write result back to destination */
@@ -66,21 +67,18 @@
}
/* set eflags:
- * ROL count affects the following flags: C
+ * ROL count affects the following flags: C, O
*/
+ bx_bool temp_CF = (result_8 & 0x01);
- set_CF(result_8 & 0x01);
- if (count == 1)
- set_OF(((op1_8 ^ result_8) & 0x80) > 0);
- }
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_8 >> 7));
}
-
void
BX_CPU_C::ROR_Eb(bxInstruction_c *i)
{
Bit8u op1_8, result_8;
- Bit8u result_b7;
unsigned count;
if (i->b1() == 0xc0)
@@ -90,7 +88,6 @@
else // 0xd2
count = CL;
-
count &= 0x07; /* use only bottom 3 bits */
/* op1 is a register or memory reference */
@@ -102,7 +99,8 @@
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
- if (count) {
+ if (! count) return;
+
result_8 = (op1_8 >> count) | (op1_8 << (8 - count));
/* now write result back to destination */
@@ -114,17 +112,15 @@
}
/* set eflags:
- * ROR count affects the following flags: C
+ * ROR count affects the following flags: C, O
*/
- result_b7 = result_8 & 0x80;
+ bx_bool result_b7 = (result_8 & 0x80) != 0;
- set_CF(result_b7 != 0);
+ set_CF(result_b7);
if (count == 1)
set_OF(((op1_8 ^ result_8) & 0x80) > 0);
- }
}
-
void
BX_CPU_C::RCL_Eb(bxInstruction_c *i)
{
@@ -138,7 +134,8 @@
else // 0xd2
count = CL;
- count = (count & 0x1F) % 9;
+ count &= 0x1F;
+ count %= 9;
/* op1 is a register or memory reference */
if (i->modC0()) {
@@ -148,29 +145,34 @@
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
+
+ if (! count) return;
- if (count) {
+ if (count==1) {
+ result_8 = (op1_8 << 1) | getB_CF();
+ }
+ else {
result_8 = (op1_8 << count) |
(getB_CF() << (count - 1)) |
(op1_8 >> (9 - count));
+ }
- /* now write result back to destination */
- if (i->modC0()) {
- BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
- }
- else {
- Write_RMW_virtual_byte(result_8);
- }
-
- /* set eflags:
- * RCL count affects the following flags: C
- */
- if (count == 1)
- set_OF(((op1_8 ^ result_8) & 0x80) > 0);
- set_CF((op1_8 >> (8 - count)) & 0x01);
+ /* now write result back to destination */
+ if (i->modC0()) {
+ BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
}
-}
+ else {
+ Write_RMW_virtual_byte(result_8);
+ }
+
+ /* set eflags:
+ * RCL count affects the following flags: C, O
+ */
+ bx_bool temp_CF = (op1_8 >> (8 - count)) & 0x01;
+ set_CF(temp_CF);
+ set_OF(temp_CF ^ (result_8 >> 7));
+}
void
BX_CPU_C::RCR_Eb(bxInstruction_c *i)
@@ -185,7 +187,8 @@
else // 0xd2
count = CL;
- count = ( count & 0x1F ) % 9;
+ count &= 0x1F;
+ count %= 9;
/* op1 is a register or memory reference */
if (i->modC0()) {
@@ -196,7 +199,8 @@
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
- if (count) {
+ if (! count) return;
+
result_8 = (op1_8 >> count) |
(getB_CF() << (8 - count)) |
(op1_8 << (9 - count));
@@ -210,16 +214,14 @@
}
/* set eflags:
- * RCR count affects the following flags: C
+ * RCR count affects the following flags: C, O
*/
set_CF((op1_8 >> (count - 1)) & 0x01);
if (count == 1)
set_OF(((op1_8 ^ result_8) & 0x80) > 0);
- }
}
-
void
BX_CPU_C::SHL_Eb(bxInstruction_c *i)
{
-------------------------------------------------------
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