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List: binutils-cvs
Subject: [binutils-gdb] x86: drop VecESize
From: Jan Beulich <jbeulich () sourceware ! org>
Date: 2018-03-28 12:25:45
Message-ID: 20180328122545.121853.qmail () sourceware ! org
[Download RAW message or body]
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c39e5b267180a5d61a6434b24bcc7888bf3c0ca7
commit c39e5b267180a5d61a6434b24bcc7888bf3c0ca7
Author: Jan Beulich <jbeulich@novell.com>
Date: Wed Mar 28 14:25:07 2018 +0200
x86: drop VecESize
It again can be inferred from other information.
The vpopcntd templates all need to have Dword added to their memory
operands; the lack thereof was actually a bug preventing certain Intel
syntax code to assemble, so test cases get extended.
Diff:
---
gas/ChangeLog | 12 +
gas/config/tc-i386.c | 26 +-
gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d | 2 +
gas/testsuite/gas/i386/avx512_vpopcntdq.d | 2 +
gas/testsuite/gas/i386/avx512_vpopcntdq.s | 2 +
gas/testsuite/gas/i386/avx512bitalg_vl-intel.d | 4 +
gas/testsuite/gas/i386/avx512bitalg_vl.d | 4 +
gas/testsuite/gas/i386/avx512bitalg_vl.s | 4 +
opcodes/ChangeLog | 8 +
opcodes/i386-gen.c | 1 -
opcodes/i386-opc.h | 7 -
opcodes/i386-opc.tbl | 1086 +-
opcodes/i386-tbl.h | 14770 +++++++++++-----------
13 files changed, 7978 insertions(+), 7950 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6e39f99..72e305d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,17 @@
2018-03-28 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (check_VecOperands): Replace uses of
+ .vecesize. Always initialize op.
+ * testsuite/gas/i386/avx512_vpopcntdq.s,
+ testsuite/gas/i386/avx512bitalg_vl.s: Add Intel syntax vpopcnt
+ broadcast cases with explicit operand size.
+ * testsuite/gas/i386/avx512_vpopcntdq.d,
+ testsuite/gas/i386/avx512_vpopcntdq-intel.d,
+ testsuite/gas/i386/avx512bitalg_vl.d
+ testsuite/gas/i386/avx512bitalg_vl-intel.d: Adjust expectations.
+
+2018-03-28 Jan Beulich <jbeulich@suse.com>
+
* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
(check_VecOperands): Re-write broadcast validation code.
(check_VecOperations): Replace BROADCAST_1TO* uses.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 0e4126e..dd7660d 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5051,17 +5051,14 @@ check_VecOperands (const insn_template *t)
i386_operand_type type, overlap;
/* Check if specified broadcast is supported in this instruction,
- and it's applied to memory operand of DWORD or QWORD type,
- depending on VecESize. */
+ and it's applied to memory operand of DWORD or QWORD type. */
op = i.broadcast->operand;
if (!t->opcode_modifier.broadcast
|| !i.types[op].bitfield.mem
- || (t->opcode_modifier.vecesize == 0
- && !i.types[op].bitfield.dword
- && !i.types[op].bitfield.unspecified)
- || (t->opcode_modifier.vecesize == 1
- && !i.types[op].bitfield.qword
- && !i.types[op].bitfield.unspecified))
+ || (!i.types[op].bitfield.unspecified
+ && (t->operand_types[op].bitfield.dword
+ ? !i.types[op].bitfield.dword
+ : !i.types[op].bitfield.qword)))
{
bad_broadcast:
i.error = unsupported_broadcast;
@@ -5069,7 +5066,7 @@ check_VecOperands (const insn_template *t)
}
operand_type_set (&type, 0);
- switch ((t->opcode_modifier.vecesize ? 8 : 4) * i.broadcast->type)
+ switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
{
case 8:
type.bitfield.qword = 1;
@@ -5116,15 +5113,16 @@ check_VecOperands (const insn_template *t)
break;
gas_assert (op < i.operands);
/* Check size of the memory operand. */
- if ((t->opcode_modifier.vecesize == 0
- && i.types[op].bitfield.dword)
- || (t->opcode_modifier.vecesize == 1
- && i.types[op].bitfield.qword))
+ if (t->operand_types[op].bitfield.dword
+ ? i.types[op].bitfield.dword
+ : i.types[op].bitfield.qword)
{
i.error = broadcast_needed;
return 1;
}
}
+ else
+ op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
/* Check if requested masking is supported. */
if (i.mask
@@ -5171,7 +5169,7 @@ check_VecOperands (const insn_template *t)
&& i.disp_encoding != disp_encoding_32bit)
{
if (i.broadcast)
- i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
+ i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
else
i.memshift = t->opcode_modifier.disp8memshift;
diff --git a/gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d \
b/gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d index d311c45..68d7424 100644
--- a/gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d
+++ b/gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d
@@ -43,6 +43,7 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 31[ ]*vpopcntd zmm6,ZMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd zmm6,ZMMWORD PTR \
\[esp\+esi\*8-0x1e240\] [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd \
zmm6,DWORD PTR \[eax\]\{1to16\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd \
zmm6,DWORD PTR \[eax\]\{1to16\} [ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ \
]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b2 00 \
20 00 00[ ]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x2000\] [ ]*[a-f0-9]+:[ ]*62 f2 7d \
48 55 72 80[ ]*vpopcntd zmm6,ZMMWORD PTR \[edx-0x2000\] @@ -57,6 +58,7 @@ \
Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 31[ ]*vpopcntq \
zmm6,ZMMWORD PTR \[ecx\] [ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ \
]*vpopcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 \
55 30[ ]*vpopcntq zmm6,QWORD PTR \[eax\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 \
30[ ]*vpopcntq zmm6,QWORD PTR \[eax\]\{1to8\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 \
7f[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 \
b2 00 20 00 00[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x2000\] [ ]*[a-f0-9]+:[ ]*62 \
f2 fd 48 55 72 80[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx-0x2000\]
diff --git a/gas/testsuite/gas/i386/avx512_vpopcntdq.d \
b/gas/testsuite/gas/i386/avx512_vpopcntdq.d index 3f10887..47c3ea8 100644
--- a/gas/testsuite/gas/i386/avx512_vpopcntdq.d
+++ b/gas/testsuite/gas/i386/avx512_vpopcntdq.d
@@ -43,6 +43,7 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 31[ ]*vpopcntd \(%ecx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd \
-0x1e240\(%esp,%esi,8\),%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd \
\(%eax\)\{1to16\},%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd \
\(%eax\)\{1to16\},%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ ]*vpopcntd \
0x1fc0\(%edx\),%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b2 00 20 00 00[ ]*vpopcntd \
0x2000\(%edx\),%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 80[ ]*vpopcntd \
-0x2000\(%edx\),%zmm6 @@ -57,6 +58,7 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 31[ ]*vpopcntq \(%ecx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntq \
-0x1e240\(%esp,%esi,8\),%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 30[ ]*vpopcntq \
\(%eax\)\{1to8\},%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 30[ ]*vpopcntq \
\(%eax\)\{1to8\},%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 7f[ ]*vpopcntq \
0x1fc0\(%edx\),%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b2 00 20 00 00[ ]*vpopcntq \
0x2000\(%edx\),%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 80[ ]*vpopcntq \
-0x2000\(%edx\),%zmm6
diff --git a/gas/testsuite/gas/i386/avx512_vpopcntdq.s \
b/gas/testsuite/gas/i386/avx512_vpopcntdq.s index 2691a46..07fcd83 100644
--- a/gas/testsuite/gas/i386/avx512_vpopcntdq.s
+++ b/gas/testsuite/gas/i386/avx512_vpopcntdq.s
@@ -39,6 +39,7 @@ _start:
vpopcntd zmm6, ZMMWORD PTR [ecx] # AVX512_VPOPCNTDQ
vpopcntd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512_VPOPCNTDQ
vpopcntd zmm6, [eax]{1to16} # AVX512_VPOPCNTDQ
+ vpopcntd zmm6, DWORD PTR [eax]{1to16} # AVX512_VPOPCNTDQ
vpopcntd zmm6, ZMMWORD PTR [edx+8128] # AVX512_VPOPCNTDQ Disp8
vpopcntd zmm6, ZMMWORD PTR [edx+8192] # AVX512_VPOPCNTDQ
vpopcntd zmm6, ZMMWORD PTR [edx-8192] # AVX512_VPOPCNTDQ Disp8
@@ -53,6 +54,7 @@ _start:
vpopcntq zmm6, ZMMWORD PTR [ecx] # AVX512_VPOPCNTDQ
vpopcntq zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512_VPOPCNTDQ
vpopcntq zmm6, [eax]{1to8} # AVX512_VPOPCNTDQ
+ vpopcntq zmm6, QWORD PTR [eax]{1to8} # AVX512_VPOPCNTDQ
vpopcntq zmm6, ZMMWORD PTR [edx+8128] # AVX512_VPOPCNTDQ Disp8
vpopcntq zmm6, ZMMWORD PTR [edx+8192] # AVX512_VPOPCNTDQ
vpopcntq zmm6, ZMMWORD PTR [edx-8192] # AVX512_VPOPCNTDQ Disp8
diff --git a/gas/testsuite/gas/i386/avx512bitalg_vl-intel.d \
b/gas/testsuite/gas/i386/avx512bitalg_vl-intel.d index d3834bd..9e2aa67 100644
--- a/gas/testsuite/gas/i386/avx512bitalg_vl-intel.d
+++ b/gas/testsuite/gas/i386/avx512bitalg_vl-intel.d
@@ -78,19 +78,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd xmm6\{k7\},XMMWORD \
PTR \[esp\+esi\*8-0x1e240\] [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ ]*vpopcntd \
xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ \
]*vpopcntd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d \
1f 55 32[ ]*vpopcntd xmm6\{k7\},DWORD PTR \[edx\]\{1to4\} [ ]*[a-f0-9]+:[ ]*62 f2 \
7d 2f 55 f5[ ]*vpopcntd ymm6\{k7\},ymm5 [ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ \
]*vpopcntd ymm6\{k7\}\{z\},ymm5 [ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe \
ff[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] [ ]*[a-f0-9]+:[ \
]*62 f2 7d 2f 55 72 7f[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] [ \
]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 7f[ ]*vpopcntd ymm6\{k7\},DWORD PTR \
\[edx\+0x1fc\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 32[ ]*vpopcntd \
ymm6\{k7\},DWORD PTR \[edx\]\{1to8\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 f5[ \
]*vpopcntq xmm6\{k7\},xmm5 [ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ ]*vpopcntq \
xmm6\{k7\}\{z\},xmm5 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe ff[ \
]*vpopcntq xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] [ ]*[a-f0-9]+:[ ]*62 f2 \
fd 0f 55 72 7f[ ]*vpopcntq xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ \
]*62 f2 fd 1f 55 72 7f[ ]*vpopcntq xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to2\} +[ \
]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 32[ ]*vpopcntq xmm6\{k7\},QWORD PTR \[edx\]\{1to2\} \
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 f5[ ]*vpopcntq ymm6\{k7\},ymm5 [ ]*[a-f0-9]+:[ \
]*62 f2 fd af 55 f5[ ]*vpopcntq ymm6\{k7\}\{z\},ymm5 [ ]*[a-f0-9]+:[ ]*62 f2 fd \
2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] \
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 72 7f[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \
\[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 72 7f[ ]*vpopcntq \
ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 32[ \
]*vpopcntq ymm6\{k7\},QWORD PTR \[edx\]\{1to4\} #pass
diff --git a/gas/testsuite/gas/i386/avx512bitalg_vl.d \
b/gas/testsuite/gas/i386/avx512bitalg_vl.d index 1f9e773..824b837 100644
--- a/gas/testsuite/gas/i386/avx512bitalg_vl.d
+++ b/gas/testsuite/gas/i386/avx512bitalg_vl.d
@@ -78,19 +78,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd \
-0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ \
]*vpopcntd 0x7f0\(%edx\),%xmm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ \
]*vpopcntd 0x1fc\(%edx\)\{1to4\},%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 32[ \
]*vpopcntd \(%edx\)\{1to4\},%xmm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 f5[ \
]*vpopcntd %ymm5,%ymm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ ]*vpopcntd \
%ymm5,%ymm6\{%k7\}\{z\} [ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe ff[ \
]*vpopcntd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 \
72 7f[ ]*vpopcntd 0xfe0\(%edx\),%ymm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 \
7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to8\},%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f \
55 32[ ]*vpopcntd \(%edx\)\{1to8\},%ymm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 \
f5[ ]*vpopcntq %xmm5,%xmm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ \
]*vpopcntq %xmm5,%xmm6\{%k7\}\{z\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe \
ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f \
55 72 7f[ ]*vpopcntq 0x7f0\(%edx\),%xmm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 \
72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to2\},%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd \
1f 55 32[ ]*vpopcntq \(%edx\)\{1to2\},%xmm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f \
55 f5[ ]*vpopcntq %ymm5,%ymm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd af 55 f5[ \
]*vpopcntq %ymm5,%ymm6\{%k7\}\{z\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 b4 f4 c0 1d fe \
ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f \
55 72 7f[ ]*vpopcntq 0xfe0\(%edx\),%ymm6\{%k7\} [ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 \
72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to4\},%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd \
3f 55 32[ ]*vpopcntq \(%edx\)\{1to4\},%ymm6\{%k7\} #pass
diff --git a/gas/testsuite/gas/i386/avx512bitalg_vl.s \
b/gas/testsuite/gas/i386/avx512bitalg_vl.s index 1b1e73e..2542b69 100644
--- a/gas/testsuite/gas/i386/avx512bitalg_vl.s
+++ b/gas/testsuite/gas/i386/avx512bitalg_vl.s
@@ -81,19 +81,23 @@ _start:
vpopcntd xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntd xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8
vpopcntd xmm6{k7}, [edx+508]{1to4} # AVX512{BITALG,VL} Disp8
+ vpopcntd xmm6{k7}, DWORD PTR [edx]{1to4} # AVX512{BITALG,VL}
vpopcntd ymm6{k7}, ymm5 # AVX512{BITALG,VL}
vpopcntd ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL}
vpopcntd ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntd ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8
vpopcntd ymm6{k7}, [edx+508]{1to8} # AVX512{BITALG,VL} Disp8
+ vpopcntd ymm6{k7}, DWORD PTR [edx]{1to8} # AVX512{BITALG,VL}
vpopcntq xmm6{k7}, xmm5 # AVX512{BITALG,VL}
vpopcntq xmm6{k7}{z}, xmm5 # AVX512{BITALG,VL}
vpopcntq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8
vpopcntq xmm6{k7}, [edx+1016]{1to2} # AVX512{BITALG,VL} Disp8
+ vpopcntq xmm6{k7}, QWORD PTR [edx]{1to2} # AVX512{BITALG,VL}
vpopcntq ymm6{k7}, ymm5 # AVX512{BITALG,VL}
vpopcntq ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL}
vpopcntq ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntq ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8
vpopcntq ymm6{k7}, [edx+1016]{1to4} # AVX512{BITALG,VL} Disp8
+ vpopcntq ymm6{k7}, QWORD PTR [edx]{1to4} # AVX512{BITALG,VL
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5b0355d..32fc1de 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,13 @@
2018-03-28 Jan Beulich <jbeulich@suse.com>
+ * i386-gen.c (opcode_modifiers): Delete VecESize.
+ * i386-opc.h (VecESize): Delete.
+ (struct i386_opcode_modifier): Delete vecesize.
+ * i386-opc.tbl: Drop VecESize.
+ * i386-tlb.h: Re-generate.
+
+2018-03-28 Jan Beulich <jbeulich@suse.com>
+
* i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
BROADCAST_1TO4, BROADCAST_1TO2): Delete.
(struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index e023795..4631611 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -638,7 +638,6 @@ static bitfield opcode_modifiers[] =
BITFIELD (NoAVX),
BITFIELD (EVex),
BITFIELD (Masking),
- BITFIELD (VecESize),
BITFIELD (Broadcast),
BITFIELD (StaticRounding),
BITFIELD (SAE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 5cf6c9e..f9a636c 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -566,12 +566,6 @@ enum
#define BOTH_MASKING 3
Masking,
- /* Input element size of vector insn:
- 0: 32bit.
- 1: 64bit.
- */
- VecESize,
-
Broadcast,
/* Static rounding control is supported. */
@@ -661,7 +655,6 @@ typedef struct i386_opcode_modifier
unsigned int noavx:1;
unsigned int evex:3;
unsigned int masking:2;
- unsigned int vecesize:1;
unsigned int broadcast:1;
unsigned int staticrounding:1;
unsigned int sae:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 18b4dcc..da57825 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2920,13 +2920,13 @@ kshiftrw, 3, 0x6630, None, 1, CpuAVX512F, \
Modrm|Vex=1|VexOpcode=2|VexW=2|IgnoreS
kunpckbw, 3, 0x664B, None, 1, CpuAVX512F, \
Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegMask, RegMask, RegMask }
-vaddpd, 3, 0x6658, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vaddpd, 3, 0x6658, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vaddpd, 4, 0x6658, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vdivpd, 3, 0x665E, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vdivpd, 3, 0x665E, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vdivpd, 4, 0x665E, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vmulpd, 3, 0x6659, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vmulpd, 3, 0x6659, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vmulpd, 4, 0x6659, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vsubpd, 3, 0x665C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vsubpd, 3, 0x665C, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vsubpd, 4, 0x665C, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
vaddps, 3, 0x58, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } @@ -2963,25 +2963,25 \
@@ vsubss, 4, 0xF35C, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVV \
valignd, 4, 0x6603, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vpternlogd, 4, \
0x6625, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-valignq, 4, 0x6603, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpternlogq, 4, 0x6625, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-
-vblendmpd, 3, 0x6665, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpblendmq, 3, 0x6664, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpermi2pd, 3, 0x6677, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpermi2q, 3, 0x6676, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpermt2pd, 3, 0x667F, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpermt2q, 3, 0x667E, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpmaxsq, 3, 0x663D, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpmaxuq, 3, 0x663F, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpminsq, 3, 0x6639, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpminuq, 3, 0x663B, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpmuldq, 3, 0x6628, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vprolvq, 3, 0x6615, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vprorvq, 3, 0x6614, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpsllvq, 3, 0x6647, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpsravq, 3, 0x6646, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpsrlvq, 3, 0x6645, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +valignq, 4, 0x6603, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpternlogq, 4, \
0x6625, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +
+vblendmpd, 3, 0x6665, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpblendmq, 3, 0x6664, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpermi2pd, 3, 0x6677, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpermi2q, 3, 0x6676, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpermt2pd, 3, 0x667F, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpermt2q, 3, 0x667E, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpmaxsq, 3, 0x663D, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpmaxuq, 3, 0x663F, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpminsq, 3, 0x6639, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpminuq, 3, 0x663B, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpmuldq, 3, 0x6628, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vprolvq, 3, 0x6615, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vprorvq, 3, 0x6614, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpsllvq, 3, 0x6647, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpsravq, 3, 0x6646, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpsrlvq, 3, 0x6645, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
vblendmps, 3, 0x6665, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vpblendmd, 3, 0x6664, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } @@ -3012,99 +3012,99 \
@@ vbroadcastss, 2, 0x6618, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1 \
vpbroadcastd, 2, 0x6658, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegXMM|Dword|Unspecified|BaseIndex, RegZMM } vpbroadcastd, 2, 0x667C, None, 1, \
CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Reg32, RegZMM }
-vcmppd, 4, 0x66C2, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmppd, 4, \
0x66C2, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmppd, 5, \
0x66C2, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, Imm8, RegZMM, RegZMM, RegMask }
-vcmpeqpd, 3, 0x66C2, 0, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpeqpd, 3, 0x66C2, \
0, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpeqpd, 4, 0x66C2, \
0, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_oqpd, 3, 0x66C2, 0, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpeq_oqpd, 3, \
0x66C2, 0, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpeq_oqpd, 4, \
0x66C2, 0, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_ospd, 3, 0x66C2, 16, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpeq_ospd, 3, \
0x66C2, 16, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpeq_ospd, 4, \
0x66C2, 16, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_uqpd, 3, 0x66C2, 8, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpeq_uqpd, 3, \
0x66C2, 8, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpeq_uqpd, 4, \
0x66C2, 8, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_uspd, 3, 0x66C2, 24, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpeq_uspd, 3, \
0x66C2, 24, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpeq_uspd, 4, \
0x66C2, 24, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpfalsepd, 3, 0x66C2, 11, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpfalsepd, 3, \
0x66C2, 11, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpfalsepd, 4, \
0x66C2, 11, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpfalse_oqpd, 3, 0x66C2, 11, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpfalse_oqpd, 3, \
0x66C2, 11, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpfalse_oqpd, 4, \
0x66C2, 11, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpfalse_ospd, 3, 0x66C2, 27, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpfalse_ospd, 3, \
0x66C2, 27, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpfalse_ospd, 4, \
0x66C2, 27, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpgepd, 3, 0x66C2, 13, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpgepd, 3, 0x66C2, \
13, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpgepd, 4, 0x66C2, \
13, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpge_oqpd, 3, 0x66C2, 29, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpge_oqpd, 3, \
0x66C2, 29, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpge_oqpd, 4, \
0x66C2, 29, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpge_ospd, 3, 0x66C2, 13, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpge_ospd, 3, \
0x66C2, 13, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpge_ospd, 4, \
0x66C2, 13, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpgtpd, 3, 0x66C2, 14, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpgtpd, 3, 0x66C2, \
14, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpgtpd, 4, 0x66C2, \
14, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpgt_oqpd, 3, 0x66C2, 30, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpgt_oqpd, 3, \
0x66C2, 30, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpgt_oqpd, 4, \
0x66C2, 30, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpgt_ospd, 3, 0x66C2, 14, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpgt_ospd, 3, \
0x66C2, 14, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpgt_ospd, 4, \
0x66C2, 14, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmplepd, 3, 0x66C2, 2, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmplepd, 3, 0x66C2, \
2, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmplepd, 4, 0x66C2, \
2, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmple_oqpd, 3, 0x66C2, 18, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmple_oqpd, 3, \
0x66C2, 18, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmple_oqpd, 4, \
0x66C2, 18, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmple_ospd, 3, 0x66C2, 2, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmple_ospd, 3, \
0x66C2, 2, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmple_ospd, 4, \
0x66C2, 2, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpltpd, 3, 0x66C2, 1, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpltpd, 3, 0x66C2, \
1, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpltpd, 4, 0x66C2, \
1, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmplt_oqpd, 3, 0x66C2, 17, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmplt_oqpd, 3, \
0x66C2, 17, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmplt_oqpd, 4, \
0x66C2, 17, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmplt_ospd, 3, 0x66C2, 1, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmplt_ospd, 3, \
0x66C2, 1, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmplt_ospd, 4, \
0x66C2, 1, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpneqpd, 3, 0x66C2, 4, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpneqpd, 3, \
0x66C2, 4, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpneqpd, 4, \
0x66C2, 4, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpneq_oqpd, 3, 0x66C2, 12, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpneq_oqpd, 3, \
0x66C2, 12, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpneq_oqpd, 4, \
0x66C2, 12, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpneq_ospd, 3, 0x66C2, 28, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpneq_ospd, 3, \
0x66C2, 28, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpneq_ospd, 4, \
0x66C2, 28, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpneq_uqpd, 3, 0x66C2, 4, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpneq_uqpd, 3, \
0x66C2, 4, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpneq_uqpd, 4, \
0x66C2, 4, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpneq_uspd, 3, 0x66C2, 20, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpneq_uspd, 3, \
0x66C2, 20, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpneq_uspd, 4, \
0x66C2, 20, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpngepd, 3, 0x66C2, 9, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpngepd, 3, \
0x66C2, 9, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpngepd, 4, \
0x66C2, 9, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnge_uqpd, 3, 0x66C2, 25, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnge_uqpd, 3, \
0x66C2, 25, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnge_uqpd, 4, \
0x66C2, 25, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnge_uspd, 3, 0x66C2, 9, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnge_uspd, 3, \
0x66C2, 9, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnge_uspd, 4, \
0x66C2, 9, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpngtpd, 3, 0x66C2, 10, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpngtpd, 3, \
0x66C2, 10, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpngtpd, 4, \
0x66C2, 10, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpngt_uqpd, 3, 0x66C2, 26, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpngt_uqpd, 3, \
0x66C2, 26, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpngt_uqpd, 4, \
0x66C2, 26, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpngt_uspd, 3, 0x66C2, 10, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpngt_uspd, 3, \
0x66C2, 10, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpngt_uspd, 4, \
0x66C2, 10, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnlepd, 3, 0x66C2, 6, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnlepd, 3, \
0x66C2, 6, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnlepd, 4, \
0x66C2, 6, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnle_uqpd, 3, 0x66C2, 22, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnle_uqpd, 3, \
0x66C2, 22, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnle_uqpd, 4, \
0x66C2, 22, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnle_uspd, 3, 0x66C2, 6, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnle_uspd, 3, \
0x66C2, 6, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnle_uspd, 4, \
0x66C2, 6, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnltpd, 3, 0x66C2, 5, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnltpd, 3, \
0x66C2, 5, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnltpd, 4, \
0x66C2, 5, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnlt_uqpd, 3, 0x66C2, 21, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnlt_uqpd, 3, \
0x66C2, 21, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnlt_uqpd, 4, \
0x66C2, 21, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpnlt_uspd, 3, 0x66C2, 5, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpnlt_uspd, 3, \
0x66C2, 5, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpnlt_uspd, 4, \
0x66C2, 5, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpordpd, 3, 0x66C2, 7, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpordpd, 3, \
0x66C2, 7, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpordpd, 4, \
0x66C2, 7, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpord_qpd, 3, 0x66C2, 7, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpord_qpd, 3, \
0x66C2, 7, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpord_qpd, 4, \
0x66C2, 7, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpord_spd, 3, 0x66C2, 23, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpord_spd, 3, \
0x66C2, 23, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpord_spd, 4, \
0x66C2, 23, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmptruepd, 3, 0x66C2, 15, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmptruepd, 3, \
0x66C2, 15, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmptruepd, 4, \
0x66C2, 15, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmptrue_uqpd, 3, 0x66C2, 15, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmptrue_uqpd, 3, \
0x66C2, 15, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmptrue_uqpd, 4, \
0x66C2, 15, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmptrue_uspd, 3, 0x66C2, 31, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmptrue_uspd, 3, \
0x66C2, 31, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmptrue_uspd, 4, \
0x66C2, 31, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpunordpd, 3, 0x66C2, 3, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpunordpd, 3, \
0x66C2, 3, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpunordpd, 4, \
0x66C2, 3, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpunord_qpd, 3, 0x66C2, 3, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpunord_qpd, 3, \
0x66C2, 3, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpunord_qpd, 4, \
0x66C2, 3, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
-vcmpunord_spd, 3, 0x66C2, 19, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } +vcmpunord_spd, 3, \
0x66C2, 19, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vcmpunord_spd, 4, \
0x66C2, 19, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, \
{ Imm8, RegZMM, RegZMM, RegMask }
vcmpps, 4, 0xC2, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } @@ -3428,13 \
+3428,13 @@ vcvtps2udq, 3, 0x79, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|Vex vsqrtps, 2, 0x51, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM } vsqrtps, 3, 0x51, None, 1, \
CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM }
-vcvtpd2dq, 2, 0xF2E6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } +vcvtpd2dq, 2, 0xF2E6, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } vcvtpd2dq, 3, 0xF2E6, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegYMM }
-vcvtpd2ps, 2, 0x665A, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } +vcvtpd2ps, 2, 0x665A, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } vcvtpd2ps, 3, 0x665A, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegYMM }
-vcvtpd2udq, 2, 0x79, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } +vcvtpd2udq, 2, 0x79, None, 1, \
CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } vcvtpd2udq, 3, 0x79, None, 1, \
CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegYMM }
vcvtph2ps, 2, 0x6613, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegYMM|YMMword|Unspecified|BaseIndex, RegZMM } @@ -3484,9 +3484,9 @@ vcvtss2si, 3, \
0xF32D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|N vcvtss2usi, 2, \
0xF379, None, 1, CpuAVX512F, \
Modrm|EVex=4|VexOpcode=0|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword, \
{ RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 } vcvtss2usi, 3, 0xF379, None, 1, \
CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegXMM, Reg32|Reg64 }
-vcvttpd2dq, 2, 0x66E6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } +vcvttpd2dq, 2, 0x66E6, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } vcvttpd2dq, 3, 0x66E6, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, RegZMM, RegYMM }
-vcvttpd2udq, 2, 0x78, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } +vcvttpd2udq, 2, 0x78, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM } vcvttpd2udq, 3, 0x78, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, RegZMM, RegYMM }
vcvttps2dq, 2, 0xF35B, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM } @@ -3526,7 +3526,7 @@ \
vextracti64x4, 3, 0x663B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode= \
vextractps, 3, 0x6617, None, 1, CpuAVX512F, \
Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } vextractps, 3, 0x6617, None, 1, \
CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegXMM, Reg64|RegMem }
-vfixupimmpd, 4, 0x6654, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfixupimmpd, 4, \
0x6654, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfixupimmpd, 5, \
0x6654, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, Imm8, RegZMM, RegZMM, RegZMM }
vfixupimmps, 4, 0x6654, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } @@ -3546,43 \
+3546,43 @@ vgetmantss, 5, 0x6627, None, 1, CpuAVX512F, \
Modrm|EVex=4|Masking=3|VexOpcode=2|V vrndscaless, 4, 0x660A, None, 1, CpuAVX512F, \
Modrm|EVex=4|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } vrndscaless, 5, 0x660A, \
None, 1, CpuAVX512F, \
Modrm|EVex=4|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, Imm8, RegXMM, RegXMM, RegXMM }
-vfmadd132pd, 3, 0x6698, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmadd132pd, 3, \
0x6698, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmadd132pd, 4, \
0x6698, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmadd213pd, 3, 0x66A8, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmadd213pd, 3, \
0x66A8, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmadd213pd, 4, \
0x66A8, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmadd231pd, 3, 0x66B8, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmadd231pd, 3, \
0x66B8, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmadd231pd, 4, \
0x66B8, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmaddsub132pd, 3, 0x6696, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmaddsub132pd, 3, \
0x6696, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmaddsub132pd, 4, \
0x6696, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmaddsub213pd, 3, 0x66A6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmaddsub213pd, 3, \
0x66A6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmaddsub213pd, 4, \
0x66A6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmaddsub231pd, 3, 0x66B6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmaddsub231pd, 3, \
0x66B6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmaddsub231pd, 4, \
0x66B6, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmsub132pd, 3, 0x669A, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmsub132pd, 3, \
0x669A, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmsub132pd, 4, \
0x669A, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmsub213pd, 3, 0x66AA, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmsub213pd, 3, \
0x66AA, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmsub213pd, 4, \
0x66AA, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmsub231pd, 3, 0x66BA, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmsub231pd, 3, \
0x66BA, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmsub231pd, 4, \
0x66BA, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmsubadd132pd, 3, 0x6697, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmsubadd132pd, 3, \
0x6697, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmsubadd132pd, 4, \
0x6697, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmsubadd213pd, 3, 0x66A7, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmsubadd213pd, 3, \
0x66A7, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmsubadd213pd, 4, \
0x66A7, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfmsubadd231pd, 3, 0x66B7, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfmsubadd231pd, 3, \
0x66B7, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfmsubadd231pd, 4, \
0x66B7, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfnmadd132pd, 3, 0x669C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfnmadd132pd, 3, \
0x669C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfnmadd132pd, 4, \
0x669C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfnmadd213pd, 3, 0x66AC, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfnmadd213pd, 3, \
0x66AC, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfnmadd213pd, 4, \
0x66AC, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfnmadd231pd, 3, 0x66BC, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfnmadd231pd, 3, \
0x66BC, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfnmadd231pd, 4, \
0x66BC, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfnmsub132pd, 3, 0x669E, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfnmsub132pd, 3, \
0x669E, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfnmsub132pd, 4, \
0x669E, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfnmsub213pd, 3, 0x66AE, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfnmsub213pd, 3, \
0x66AE, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfnmsub213pd, 4, \
0x66AE, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vfnmsub231pd, 3, 0x66BE, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vfnmsub231pd, 3, \
0x66BE, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vfnmsub231pd, 4, \
0x66BE, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vscalefpd, 3, 0x662C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vscalefpd, 3, 0x662C, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vscalefpd, 4, 0x662C, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
vfmadd132ps, 3, 0x6698, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } @@ -3690,7 +3690,7 @@ \
vpgatherdd, 2, 0x6690, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Vex \
vgatherqps, 2, 0x6693, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ YMMword|Unspecified|BaseIndex, RegYMM } vpgatherqd, 2, 0x6691, None, 1, \
CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ YMMword|Unspecified|BaseIndex, RegYMM }
-vgetexppd, 2, 0x6642, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } +vgetexppd, 2, 0x6642, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } vgetexppd, 3, 0x6642, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, RegZMM, RegZMM }
vgetexpps, 2, 0x6642, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM } @@ -3702,9 +3702,9 @@ \
vgetexpsd, 4, 0x6643, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=1|Ve \
vgetexpss, 3, 0x6643, None, 1, CpuAVX512F, \
Modrm|EVex=4|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } vgetexpss, 4, 0x6643, None, \
1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, RegXMM, RegXMM, RegXMM }
-vgetmantpd, 3, 0x6626, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } +vgetmantpd, 3, 0x6626, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } vgetmantpd, 4, 0x6626, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, Imm8, RegZMM, RegZMM }
-vrndscalepd, 3, 0x6609, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } +vrndscalepd, 3, 0x6609, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } vrndscalepd, 4, 0x6609, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, Imm8, RegZMM, RegZMM }
vgetmantps, 3, 0x6626, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM } @@ -3720,9 +3720,9 @@ \
vinserti64x4, 4, 0x663A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2
vinsertps, 4, 0x6621, None, 1, CpuAVX512F, \
Modrm|EVex=4|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vmaxpd, 3, 0x665F, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vmaxpd, 3, 0x665F, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vmaxpd, 4, 0x665F, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
-vminpd, 3, 0x665D, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vminpd, 3, 0x665D, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vminpd, 4, 0x665D, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, \
{ Imm8, RegZMM, RegZMM, RegZMM }
vmaxps, 3, 0x5F, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } @@ -3812,9 +3812,9 @@ \
vpabsd, 2, 0x661E, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW= \
vrcp14ps, 2, 0x664C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM } vrsqrt14ps, 2, 0x664E, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM }
-vpabsq, 2, 0x661F, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM }
-vrcp14pd, 2, 0x664C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM }
-vrsqrt14pd, 2, 0x664E, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } +vpabsq, 2, 0x661F, None, 1, \
CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } +vrcp14pd, 2, 0x664C, None, 1, \
CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM } +vrsqrt14pd, 2, 0x664E, None, \
1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM }
vpaddd, 3, 0x66FE, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vpandd, 3, 0x66DB, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } @@ -3825,17 +3825,17 \
@@ vpunpckhdq, 3, 0x666A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|V \
vpunpckldq, 3, 0x6662, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } vpxord, 3, 0x66EF, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpaddq, 3, 0x66D4, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpandnq, 3, 0x66DF, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpandq, 3, 0x66DB, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpmuludq, 3, 0x66F4, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vporq, 3, 0x66EB, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpsubq, 3, 0x66FB, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpunpckhqdq, 3, 0x666D, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpunpcklqdq, 3, 0x666C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vpxorq, 3, 0x66EF, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vunpckhpd, 3, 0x6615, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vunpcklpd, 3, 0x6614, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpaddq, 3, 0x66D4, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpandnq, 3, 0x66DF, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpandq, 3, 0x66DB, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpmuludq, 3, 0x66F4, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vporq, 3, 0x66EB, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpsubq, 3, 0x66FB, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpunpckhqdq, 3, \
0x666D, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpunpcklqdq, 3, \
0x666C, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vpxorq, 3, 0x66EF, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vunpckhpd, 3, 0x6615, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vunpcklpd, 3, 0x6614, \
None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
vpbroadcastq, 2, 0x6659, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegXMM|Qword|Unspecified|BaseIndex, RegZMM } vpbroadcastq, 2, 0x667C, None, 1, \
CpuAVX512F|Cpu64, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ Reg64, RegZMM } @@ -3857,37 +3857,37 @@ vpcmpnequd, 3, 0x661E, 4, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=2|VexV vpcmpnleud, 3, 0x661E, 6, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask } vpcmpnltud, 3, \
0x661E, 5, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, \
{ RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpeqq, 3, 0x6629, None, 1, CpuAVX512F, \
Modrm|EVex=1|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, \
{ RegZMM|Qword|ZMMword|Unsp[...]
[diff truncated at 100000 bytes]
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