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List:       axp-redhat
Subject:    Re: LX164 and rpcc
From:       Hannu Mallat <hmallat () peak3 ! cs ! hut ! fi>
Date:       1998-12-29 14:03:57
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On Sat, 26 Dec 1998 Jay.Estabrook@digital.com wrote:

> One can successfully build/link MILO *ONLY* under RH 4.2, unless you want
> to use the free x86 BIOS emulator (not recommended for most VGA cards).

Ok, I threw in RH 4.2 on another partition and got a working milo. I
managed to get reasonable-looking PCC values even after a munmap() by
modifying palcode/lx164/osfpal.S as follows:

[root@peak9 lx164]# diff -c osfpal.S.old osfpal.S
*** osfpal.S.old        Wed Dec 28 17:46:35 2078
--- osfpal.S    Tue Dec 29 14:09:18 1998
***************
*** 2042,2048 ****
        mfpr    v0, ptPcbb              // Get current PCBB
  
        ldq_p   t8, PCB_Q_FEN(a0)       // Get new FEN
-       ldq_p   t9, PCB_L_PCC(a0)       // Get new ASN 
  
        srl     p5, 32, p7              // Move CC<OFFSET> to low longword
        mfpr    t10, ptUsp              // Get the user stack pointer
--- 2042,2047 ----
***************
*** 2064,2069 ****
--- 2063,2069 ----
        mfpr    p7, icsr                // Get current ICSR value
  
        and     t8, 1, t8               // Clean new FEN value to single bit
+       sll     t8, ICSR_V_FPE, t8      // Shift new FEN into position
        br      zero, CallPal_SwpCtxCont
  

  /*
***************
*** 3402,3410 ****
        ALIGN_BLOCK
  
  CallPal_SwpCtxCont:
-       sll     t8, ICSR_V_FPE, t8      // Shift new FEN into position
        bic     p7, t10, p7             // Clean ISR<FPE> 
  
        srl     t9, 32, t10             // Move ASN to low longword
        ldq_p   p6, PCB_Q_PTBR(a0)      // Get the new page table base
  
--- 3402,3410 ----
        ALIGN_BLOCK
  
  CallPal_SwpCtxCont:
        bic     p7, t10, p7             // Clean ISR<FPE> 
  
+       ldq_p   t9, PCB_L_PCC(a0)       // Get new ASN 
        srl     t9, 32, t10             // Move ASN to low longword
        ldq_p   p6, PCB_Q_PTBR(a0)      // Get the new page table base
  
I suppose there were some instruction scheduling issues that decided
the original placing of ldq_p t9, but I wouldn't know anything about 
that, so I just placed it near the point of use.

I haven't yet properly validated the PCC values after my patch: they seem 
to be in the right order of magnitude ;-)

Hannu


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